Ryan1234 said:
When the metal 2 is fabricated, does the accumulated charges in different parts of metal 1 will convene through the jumpers ?
In that way, the total charges on the gate oxide won't change, so the gate oxide will be harmed.
You're totally right: Shortly before the end of metal_2 etching, when all metal_2 areas are already separated and the connection between the metal_2 - via - metal_1 - contact - poly-gate is complete, the metal_2 parts of these connections catch charges from the ion beam, which will be distributed over the
total connection. The metal_2 ARC (antenna rules' check) will check the ratio of the
total connection area (from metal_2 to poly, which stores the caught charge) to the gate area, and if this ratio exceeds a certain limit (fixed by the foundry), it will flag an error.
So in this case "hopping" only between metal_1 & metal_2 won't help; it is necessary to hop up to a metal level where the fully completed individual wire connection guarantees access to a silicon region, mostly an inverter-like output and/or an ESD structure. So you simply must make sure, that at
any metal-level etching the (until then) total connection area doesn't exceed the a.m. ratio limit. This should be possible, if you hop - not too far away from the gate(s) - to the highest metal level (used by the individual connection) and return to the original/required level.
Routing wires without any connection to silicon are seldom (because gate inputs usually are supplied by outputs), but not impossible, however: e.g. think of a series connection between a poly or MIM capacitor and a gate input.
If there is no contact to silicon (junction) at
any metal level, you must provide a (normally) reverse-biased (minimum area) junction diode to the substrate (GND) or (better for draining off positive charges) to an n-well (VDD).