sear
Newbie level 4
hv cmos layout
I am drawing layout with AMS 50V high voltage CMOS process and I am using calibre from verification. I found one problem when I do DRC check.
I draw two inverters by connection the output of the first one to the input of the second one. I used nmos20hs and pmos20hs devices. I always got DRC errors saying that the gate of the second inverter is floating. Actually it is connected to the output of the first inverter. I tried LVS, the layout and the schematic matches.
I also tried to implemented the inverters with other devices like nmos20h and pmos20h. The DRC errors disappeared. It seems that calibre does not consider nmos20hs and pmos20hs as transistors and it got wrong results.
Anyone have ever used these symmetrical devices? How could we remove these DRC errors?
Thanks a lot.
I am drawing layout with AMS 50V high voltage CMOS process and I am using calibre from verification. I found one problem when I do DRC check.
I draw two inverters by connection the output of the first one to the input of the second one. I used nmos20hs and pmos20hs devices. I always got DRC errors saying that the gate of the second inverter is floating. Actually it is connected to the output of the first inverter. I tried LVS, the layout and the schematic matches.
I also tried to implemented the inverters with other devices like nmos20h and pmos20h. The DRC errors disappeared. It seems that calibre does not consider nmos20hs and pmos20hs as transistors and it got wrong results.
Anyone have ever used these symmetrical devices? How could we remove these DRC errors?
Thanks a lot.