A question about a differential amplifier design.

[eddsos]

Hello, using the follow spice netlist, V(6) = 0V when VID = 0V.
But, what if I want V(6) = 1V when VID =0V. Which parameters should be adjusted? I changed VIC, but this seems have no effect.

Thanks

*
*.lib 'E:\software\asmc\models\IC5.1.41\hspice\bc35hv_mod_hspice.lib' MOS_TT
*
VID 7 0 DC 0V AC 1V
E+ 1 10 7 0 0.5
E- 2 10 7 0 -0.5
VIC 10 0 DC 0.65
VDD 3 0 DC 2.5V
VSS 4 0 DC -2.5V
M1 5 1 8 8 NMOS1 W=9.6u L=5.4u m=1
M2 6 2 8 8 NMOS1 W=9.6u L=5.4u m=1
M3 5 5 3 3 PMOS1 W=25.8u L=5.4u m=1
M4 6 5 3 3 PMOS1 W=25.8u L=5.4u m=1
M5 8 9 4 4 NMOS1 W=21.6u L=1.2u m=1
M6 9 9 4 4 NMOS1 W=21.6u L=1.2u m=1
IB 3 9 220uA
*
.MODEL NMOS1 NMOS VTO=1 KP=40U
+ GAMMA=1.0 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.MODEL PMOS1 PMOS VTO=-1 KP=15U
+ GAMMA=0.6 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
* ANALYSIS
.DC VID -2.5 2.5 0.05
.TF V(6) VID
.PROBE I(*)
.END

Added after 5 hours 3 minutes:

the attachment is the schematic[/img]

 

[sudheerkm]

check bias point u may b pegged at rails
try .op
and see dc conditions