spman
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Hi,
I encountered a wonderful problem while I was doing post-route simulation! The design is a particular DDR3 controller for ML605 (virtex-6) that I downloaded at Xilinx. After a little modifications, I prepared it for writing and reading some data to test the controller. The design works correctly in behavioral simulation. But not in post-route simulation!
There is a parameter namely SIM_BYPASS_INIT_CAL.
I assigned it 'FAST' to skip initialization and calibration. But according to my observations, it seems the design is waiting in post-route simulation!
Is it possible that the parameter is automatically changed while doing implementation? Is it anyway to see parameters in post-route simulation?
I encountered a wonderful problem while I was doing post-route simulation! The design is a particular DDR3 controller for ML605 (virtex-6) that I downloaded at Xilinx. After a little modifications, I prepared it for writing and reading some data to test the controller. The design works correctly in behavioral simulation. But not in post-route simulation!
There is a parameter namely SIM_BYPASS_INIT_CAL.
Code:
parameter SIM_BYPASS_INIT_CAL = "FAST",
// # = "OFF" - Complete memory init &
// calibration sequence
// # = "SKIP" - Skip memory init &
// calibration sequence
// # = "FAST" - Skip memory init & use
// abbreviated calib sequence
Is it possible that the parameter is automatically changed while doing implementation? Is it anyway to see parameters in post-route simulation?