Teg-Men
Junior Member level 2
I want to write "8" on a monitor. I have some codes. Xilinx says everything is OK. There is no error or warning. However, when I connect my Basys2 to VGA Connector, Monitor says " attention, there is no signal". Here is my codes:
CODE FOR VGA CONTROLLER:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
use UNISIM.VComponents.all;
entity vga_controller_800_60 is
port(
rst : in std_logic;
pixel_clk : in std_logic;
HS : out std_logic;
VS : out std_logic;
red : out std_logic ;
green : out std_logic;
blue : out std_logic;
blank : out std_logic
);
end vga_controller_800_60;
architecture Behavioral of vga_controller_800_60 is
component clock40
port(clkin: in std_logic;
clkout: out std_logic);
end component;
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- maximum value for the horizontal pixel counter
constant HMAX : std_logic_vector(10 downto 0) := "10000100000"; -- 1056
-- maximum value for the vertical pixel counter
constant VMAX : std_logic_vector(10 downto 0) := "01001110100"; -- 628
-- total number of visible columns
constant HLINES: std_logic_vector(10 downto 0) := "01100100000"; -- 800
-- value for the horizontal counter where front porch ends
constant HFP : std_logic_vector(10 downto 0) := "01101001000"; -- 840
-- value for the horizontal counter where the synch pulse ends
constant HSP : std_logic_vector(10 downto 0) := "01111001000"; -- 968
-- total number of visible lines
constant VLINES: std_logic_vector(10 downto 0) := "01001011000"; -- 600
-- value for the vertical counter where the front porch ends
constant VFP : std_logic_vector(10 downto 0) := "01001011001"; -- 601
-- value for the vertical counter where the synch pulse ends
constant VSP : std_logic_vector(10 downto 0) := "01001011101"; -- 605
-- polarity of the horizontal and vertical synch pulse
-- only one polarity used, because for this resolution they coincide.
constant SPP : std_logic := '1';
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- horizontal and vertical counters
signal hcounter : std_logic_vector(10 downto 0) := "00000000000";
signal vcounter : std_logic_vector(10 downto 0) := "00000000000";
-- active when inside visible screen area.
signal video_enable: std_logic;
begin
red <= '0';
green <= '0';
-- output horizontal and vertical counters
--hcount <= hcounter;
--vcount <= vcounter;
-- blank is active when outside screen visible area
-- color output should be blacked (put on 0) when blank in active
-- blank is delayed one pixel clock period from the video_enable
-- signal to account for the pixel pipeline delay.
blank <= not video_enable when rising_edge(pixel_clk);
-- increment horizontal counter at pixel_clk rate
-- until HMAX is reached, then reset and keep counting
h_count: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(rst = '1') then
hcounter <= (others => '0');
elsif(hcounter = HMAX) then
hcounter <= (others => '0');
else
hcounter <= hcounter + 1;
end if;
end if;
end process h_count;
-- increment vertical counter when one line is finished
-- (horizontal counter reached HMAX)
-- until VMAX is reached, then reset and keep counting
v_count: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(rst = '1') then
vcounter <= (others => '0');
elsif(hcounter = HMAX) then
if(vcounter = VMAX) then
vcounter <= (others => '0');
else
vcounter <= vcounter + 1;
end if;
end if;
end if;
end process v_count;
-- generate horizontal synch pulse
-- when horizontal counter is between where the
-- front porch ends and the synch pulse ends.
-- The HS is active (with polarity SPP) for a total of 128 pixels.
do_hs: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(hcounter >= HFP and hcounter < HSP) then
HS <= SPP;
else
HS <= not SPP;
end if;
end if;
end process do_hs;
-- generate vertical synch pulse
-- when vertical counter is between where the
-- front porch ends and the synch pulse ends.
-- The VS is active (with polarity SPP) for a total of 4 video lines
-- = 4*HMAX = 4224 pixels.
do_vs: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(vcounter >= VFP and vcounter < VSP) then
VS <= SPP;
else
VS <= not SPP;
end if;
end if;
end process do_vs;
-- enable video output when pixel is in visible area
video_enable <= '1' when (hcounter < HLINES and vcounter < VLINES) else '0';
-- yazalım
process(pixel_clk)
begin
if (rising_edge(pixel_clk)) then
if(hcounter >= "00100101100")
and(hcounter < "00111110100")
and(vcounter = "00001111000") then
blue <= '1';
elsif(hcounter >= "00100101100")
and(hcounter < "00111110100")
and(vcounter = "00100101100") then
blue <= '1';
elsif(hcounter >= "00100101100")
and(hcounter < "00111110100")
and(vcounter = "00111100000") then
blue <= '1';
elsif(vcounter >= "00001111000")
and(vcounter < "00111100000")
and(hcounter = "00100101100") then
blue <= '1';
elsif(vcounter >= "00001111000")
and(vcounter < "00111100000")
and(hcounter = "00111110100") then
blue <= '1';
else
blue <= '0';
end if;
end if;
end process;
end Behavioral;
And clock:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clock40 is
port(clkin: in std_logic;
clkout: out std_logic);
end clock40;
architecture Behavioral of clock40 is
begin
process(clkin)
variable count: integer range 0 to 99;
begin
if(clkin'event and clkin='1') then
if(count < 25) then
clkout <= '1';
count:= count + 1;
elsif(24 < count and count <50) then
clkout <= '0';
count:= count + 1;
elsif(49 < count and count <75) then
clkout <= '1';
count:= count + 1;
elsif(74 < count and count <99) then
clkout <= '0';
count:= count + 1;
else
clkout <= '0';
count:= 0;
end if;
end if;
end process;
clockdivider2 : clock40
port map ( clkin => CLK,
clkout => CLK_40MHz);
end Behavioral;
And here is my pin assignment:
# Pin assignment for pushbutton switches
NET "RST" LOC = "a7";
# Pin assignment for clock
NET "CLK" LOC = "b8";
# Pin assignment for VGA
NET "RED" LOC = "c14";
NET "GREEN" LOC = "g13";
NET "BLUE" LOC = "h13";
NET "VS" LOC = "k13";
NET "HS" LOC = "j14";
These codes may show a "8" on the monitor. But they do not. Monitor recognizes my basys2 but it says no signal is received. Do you have any idea about where is the problem?
Thank you;
CODE FOR VGA CONTROLLER:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
use UNISIM.VComponents.all;
entity vga_controller_800_60 is
port(
rst : in std_logic;
pixel_clk : in std_logic;
HS : out std_logic;
VS : out std_logic;
red : out std_logic ;
green : out std_logic;
blue : out std_logic;
blank : out std_logic
);
end vga_controller_800_60;
architecture Behavioral of vga_controller_800_60 is
component clock40
port(clkin: in std_logic;
clkout: out std_logic);
end component;
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- maximum value for the horizontal pixel counter
constant HMAX : std_logic_vector(10 downto 0) := "10000100000"; -- 1056
-- maximum value for the vertical pixel counter
constant VMAX : std_logic_vector(10 downto 0) := "01001110100"; -- 628
-- total number of visible columns
constant HLINES: std_logic_vector(10 downto 0) := "01100100000"; -- 800
-- value for the horizontal counter where front porch ends
constant HFP : std_logic_vector(10 downto 0) := "01101001000"; -- 840
-- value for the horizontal counter where the synch pulse ends
constant HSP : std_logic_vector(10 downto 0) := "01111001000"; -- 968
-- total number of visible lines
constant VLINES: std_logic_vector(10 downto 0) := "01001011000"; -- 600
-- value for the vertical counter where the front porch ends
constant VFP : std_logic_vector(10 downto 0) := "01001011001"; -- 601
-- value for the vertical counter where the synch pulse ends
constant VSP : std_logic_vector(10 downto 0) := "01001011101"; -- 605
-- polarity of the horizontal and vertical synch pulse
-- only one polarity used, because for this resolution they coincide.
constant SPP : std_logic := '1';
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- horizontal and vertical counters
signal hcounter : std_logic_vector(10 downto 0) := "00000000000";
signal vcounter : std_logic_vector(10 downto 0) := "00000000000";
-- active when inside visible screen area.
signal video_enable: std_logic;
begin
red <= '0';
green <= '0';
-- output horizontal and vertical counters
--hcount <= hcounter;
--vcount <= vcounter;
-- blank is active when outside screen visible area
-- color output should be blacked (put on 0) when blank in active
-- blank is delayed one pixel clock period from the video_enable
-- signal to account for the pixel pipeline delay.
blank <= not video_enable when rising_edge(pixel_clk);
-- increment horizontal counter at pixel_clk rate
-- until HMAX is reached, then reset and keep counting
h_count: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(rst = '1') then
hcounter <= (others => '0');
elsif(hcounter = HMAX) then
hcounter <= (others => '0');
else
hcounter <= hcounter + 1;
end if;
end if;
end process h_count;
-- increment vertical counter when one line is finished
-- (horizontal counter reached HMAX)
-- until VMAX is reached, then reset and keep counting
v_count: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(rst = '1') then
vcounter <= (others => '0');
elsif(hcounter = HMAX) then
if(vcounter = VMAX) then
vcounter <= (others => '0');
else
vcounter <= vcounter + 1;
end if;
end if;
end if;
end process v_count;
-- generate horizontal synch pulse
-- when horizontal counter is between where the
-- front porch ends and the synch pulse ends.
-- The HS is active (with polarity SPP) for a total of 128 pixels.
do_hs: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(hcounter >= HFP and hcounter < HSP) then
HS <= SPP;
else
HS <= not SPP;
end if;
end if;
end process do_hs;
-- generate vertical synch pulse
-- when vertical counter is between where the
-- front porch ends and the synch pulse ends.
-- The VS is active (with polarity SPP) for a total of 4 video lines
-- = 4*HMAX = 4224 pixels.
do_vs: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(vcounter >= VFP and vcounter < VSP) then
VS <= SPP;
else
VS <= not SPP;
end if;
end if;
end process do_vs;
-- enable video output when pixel is in visible area
video_enable <= '1' when (hcounter < HLINES and vcounter < VLINES) else '0';
-- yazalım
process(pixel_clk)
begin
if (rising_edge(pixel_clk)) then
if(hcounter >= "00100101100")
and(hcounter < "00111110100")
and(vcounter = "00001111000") then
blue <= '1';
elsif(hcounter >= "00100101100")
and(hcounter < "00111110100")
and(vcounter = "00100101100") then
blue <= '1';
elsif(hcounter >= "00100101100")
and(hcounter < "00111110100")
and(vcounter = "00111100000") then
blue <= '1';
elsif(vcounter >= "00001111000")
and(vcounter < "00111100000")
and(hcounter = "00100101100") then
blue <= '1';
elsif(vcounter >= "00001111000")
and(vcounter < "00111100000")
and(hcounter = "00111110100") then
blue <= '1';
else
blue <= '0';
end if;
end if;
end process;
end Behavioral;
And clock:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clock40 is
port(clkin: in std_logic;
clkout: out std_logic);
end clock40;
architecture Behavioral of clock40 is
begin
process(clkin)
variable count: integer range 0 to 99;
begin
if(clkin'event and clkin='1') then
if(count < 25) then
clkout <= '1';
count:= count + 1;
elsif(24 < count and count <50) then
clkout <= '0';
count:= count + 1;
elsif(49 < count and count <75) then
clkout <= '1';
count:= count + 1;
elsif(74 < count and count <99) then
clkout <= '0';
count:= count + 1;
else
clkout <= '0';
count:= 0;
end if;
end if;
end process;
clockdivider2 : clock40
port map ( clkin => CLK,
clkout => CLK_40MHz);
end Behavioral;
And here is my pin assignment:
# Pin assignment for pushbutton switches
NET "RST" LOC = "a7";
# Pin assignment for clock
NET "CLK" LOC = "b8";
# Pin assignment for VGA
NET "RED" LOC = "c14";
NET "GREEN" LOC = "g13";
NET "BLUE" LOC = "h13";
NET "VS" LOC = "k13";
NET "HS" LOC = "j14";
These codes may show a "8" on the monitor. But they do not. Monitor recognizes my basys2 but it says no signal is received. Do you have any idea about where is the problem?
Thank you;