Hi, gerade, when we synthesis our design, we usually use power compile to insert clock gating. It can reduce the power consume.
So i mean not using clock gating but using oprand isolation method. This method conflict with Clock Gating in usuallly because inserting clock gating is introduced before operand isolation. And more some engineers told me that it could increase area when using the operand isolation method in synthesis. So i doubt that we could use the method in synthesis? I don't want increase area of my design and want reduce power consume.