A net is not a legal lvalue in this context!! Help

[Harishddixit]

Hi All ,

Obtaining the following error when compiling the code mentioned below the error :

Error :

Data=$urandom;
|
ncvlog: *E,WANOTL (code.sv,133|5): A net is not a legal lvalue in this context [9.3.1(IEEE)].
module worklib.checker:sv
errors: 1, warnings: 0
irun: *E,VLGERR: An error occurred during parsing. Review the log file for errors with the code *E and fix those identified problems to proceed. Exiting with code (status 1).

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Code Verilog - [expand]
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module checker( output logic Clock, Reset, Enable,UpDn , output reg Load, input reg [7:0] Data , input reg [7:0] Q );
          
     reg [7:0]temp;
     assign Q = (temp);
         
    initial
    begin
    Clock = 0;
        forever #10 Clock = ~Clock;
        #1000 $finish;
    end
 
    initial
   begin
    temp=0;
   end
 
    always @ (posedge Clock)
  begin         
        Reset=1;
        #10 Reset=0;
        Enable=1;
        Load=$urandom;
        UpDn=1;
        Data=$random;
    
    
 end
endmodule

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Please help how to fix the issue, Beginner here

 

[jbeniston]

You have Data as an input, and are trying to assign something to it.

 

[sharath666]

Moreover, I don't know what is this "input reg".....