A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits

[Manigandan BVS]

can anyone pls give an idea regarding soft error,redundancy addition and removal and their implementation in vhdl....

 

[dick_freebird]

In VHDL, I don't have any good idea. But I can suggest
you use your friend Google to look for "single event upset
design harden" for more general information on methods.

There's more to it than just trying to duplicate and vote
everything. You have to have a way to check the design
for things like state-machine (incl counter) states that
have no path back to normal (like, a /10 counter that
gets kicked to 13 - what's the outcome?). And you may
prefer to develop a library with a high degree of natural
immunity, rather than triple up on every gate in the data
path, and so on.

IEEE NSREC conference always has stuff about this, so
will some of the memory and processor design confabs
(to lesser extent). All stuck behind a pay wall because
IEEE is a money extraction, not a member service org.