abhijitdutta2005
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My circuit works at 5V LS TTL level. The power supply is derived from 2200V AC, 50Hz ->12V down to 5V using 7805 regulator and 470uF+ 0.1uF filter capacitors. The supply has less than 100mV noise.Any time there is a low to high transition in my logic circuit, always there's a glitch of 1mS. The high to low is always clean. The glitch actually reaches 5V. I see a clear triangle of width 1mS.
If I put an RC to damp the rise time, the next stage of logic this re-appears. Can anyone help? Attached a simple picture. I tried putting a re-triggerable 555 monoshot. but it does not help. Any time there's a low to high transition, this glitch appears. It's not oscilloscope issue, as I put this through a shift register (LS164) there is see clearly a shift of 2. I put this pulse to a D-FF (LS74) with D input ties high and strangely the Q output going low to high also shows this, whereas, the first edge of glitch having brought Q to high should not have changed the output when the second rising edge of clock comes...
If I put an RC to damp the rise time, the next stage of logic this re-appears. Can anyone help? Attached a simple picture. I tried putting a re-triggerable 555 monoshot. but it does not help. Any time there's a low to high transition, this glitch appears. It's not oscilloscope issue, as I put this through a shift register (LS164) there is see clearly a shift of 2. I put this pulse to a D-FF (LS74) with D input ties high and strangely the Q output going low to high also shows this, whereas, the first edge of glitch having brought Q to high should not have changed the output when the second rising edge of clock comes...