Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

A glitch on low to high transistion

Status
Not open for further replies.
Newbie level 3
Joined
Apr 6, 2013
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,322
My circuit works at 5V LS TTL level. The power supply is derived from 2200V AC, 50Hz ->12V down to 5V using 7805 regulator and 470uF+ 0.1uF filter capacitors. The supply has less than 100mV noise.Any time there is a low to high transition in my logic circuit, always there's a glitch of 1mS. The high to low is always clean. The glitch actually reaches 5V. I see a clear triangle of width 1mS.
If I put an RC to damp the rise time, the next stage of logic this re-appears. Can anyone help? Attached a simple picture. I tried putting a re-triggerable 555 monoshot. but it does not help. Any time there's a low to high transition, this glitch appears. It's not oscilloscope issue, as I put this through a shift register (LS164) there is see clearly a shift of 2. I put this pulse to a D-FF (LS74) with D input ties high and strangely the Q output going low to high also shows this, whereas, the first edge of glitch having brought Q to high should not have changed the output when the second rising edge of clock comes...
 

There is no picture attached. Glitches can came from inadequate bypassing of the power supply pins of the TTL chips or a "ground bounce" . Although 1mS (milliseconds) is too width for that. Are you sure that is not uS (microseconds) ?
You should check for long wires and ground loops which add inductance and make the VCC and GND pins noisy.
Add bypass capacitors as close as possible to the chips. And assure good grounding.
 

Sorry. Somehow the picture didn't get attached. As I said, there's adequate filtering and "470uF+ 0.1uF filter capacitors. The supply has less than 100mV noise."
Also, I would expect ground bounce when circuits draws (sinks) current, i.e., when logic switches from high to low. This problem is just the reverse. Whenever there's low to high (when TTL driver transistors are switching off) that time I see this. It is 1ms width, not ns. In DSO I store and expand to see it is a nice triangle pulse reaching almost 5V, then it rises to proper high level. My power supply is 1Amp and I am drawing very little current (mA).

There is no picture attached. Glitches can came from inadequate bypassing of the power supply pins of the TTL chips or a "ground bounce" . Although 1mS (milliseconds) is too width for that. Are you sure that is not uS (microseconds) ?
You should check for long wires and ground loops which add inductance and make the VCC and GND pins noisy.
Add bypass capacitors as close as possible to the chips. And assure good grounding.
 

Attachments

  • glitch.jpg
    glitch.jpg
    21.2 KB · Views: 47

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top