A Fundamental Verilog Question on Assignment Statement

[billmcgill2]

Hi guys, I have a question here.
Quite urgent; I really appreciate if you can help.

Suppose three variables:

reg [31:0] A;
reg [31:0] B;
reg [31:0] C;

Do you know what does the following two assignment statements mean?
if (...)
begin
C=(1);
A=(B);
end

Thank you very much!

 

[permute]

C = (1); // C = 1. (1) = 1. in verilog, this is valid, and would assign C with 0x00000001
C = (B); // C = B. (B) = B. this is valid.

Keep in mind that both use blocking assigns, and thus are only appropriate if the always block describes only combinatorial logic, or is only used for simulation purposes.