A few PLL / VCO Questions

[arefeidi]

kd pll gain

Hi,

I've got a few questions regarding PLL's and VCO's. In my project I'm going to use a synthesizer like the ADF4111 from Analog Devices. Output frequency about 900MHz (ZComm or Minicircuits VCO), crystal oscillator 10 MHz (if that's of interest).

1. Which frequency are the charge pump impulses - I suppose (f_vco / N). Am I right? So when I double the divider N, the rate of the impulses changes gets halved?
2. The output resistance of the synthesizers charge pump (current source) should be as large as possible, right? Is it usually big enough to be able to calculate with an output resistance of ∞ (infinite)?
3. What is the usual input impedance for a VCO (for the tuning voltage input)?

Thanks in advance for any help!

 

[arefeidi]

vco kvco loop filter size

The problem why I'm asking this, is, that I've problems in understanding how to dimension the loop filter of a charge pump pll.

In the ADF4111 datasheet ( -> https://www.analog.com/static/imported-files/data_sheets/ADF4110_4111_4112_4113.pdf) some examples are given (e.g. on page 22). I've attached the schematics of this example.

For the attached picture they say: "Loop Bandwidth = 20 kHz"
I've simulated the loop-filter as standalone - but the bandwidth of the filter is nowhere near 20 kHz, it's much lower.
What am I doing wrong?


P.S. I know I also have to consider the phase detector gain KD and the VCO gain KVCO to calculate the loop bandwidth. Though, as far as I understood it right, both KD and KVCO definitely do NOT increase the loop bandwidth. So if the filter bandwidth is already below those 20 kHz, how can the overall loop bandwidth be 20 kHz??

 

[LvW]

pll vco

Quote:I know I also have to consider the phase detector gain KD and the VCO gain KVCO to calculate the loop bandwidth. Though, as far as I understood it right, both KD and KVCO definitely do NOT increase the loop bandwidth. So if the filter bandwidth is already below those 20 kHz, how can the overall loop bandwidth be 20 kHz??

Since KD and Kvco determine the natural frequency, both parameters also influence the BW of the loop.

 

[arefeidi]

m/a-com vco

Quote:I know I also have to consider the phase detector gain KD and the VCO gain KVCO to calculate the loop bandwidth. Though, as far as I understood it right, both KD and KVCO definitely do NOT increase the loop bandwidth. So if the filter bandwidth is already below those 20 kHz, how can the overall loop bandwidth be 20 kHz??

Since KD and Kvco determine the natural frequency, both parameters also influence the BW of the loop.

Influence yes, but what I've read so far KD and Kvco both act as a lowpass, so they can only decrease the overall bandwidth of the loop - and not increase it. In other words: The overall loop bandwidth is always smaller than the filter bandwidth: BW_loop > BW_filter
If I now want a loop bandwidth of let's say 20 kHz, I've got to choose the filter bandwidth somewhere above 20 kHz.

Did I misunderstand something there?



Somehow I've got the feeling I'm thinking ways too complicated...

 

[LvW]

pll zero bode plot

KD as well as Kvco both are constants which define the sensitivity of the PD resp. the VCO. Thus, of course, they are not frequency dependent; where have you read they would act as a low pass ?

 

[fred23]

adi pll opamp

Quote:I know I also have to consider the phase detector gain KD and the VCO gain KVCO to calculate the loop bandwidth. Though, as far as I understood it right, both KD and KVCO definitely do NOT increase the loop bandwidth. So if the filter bandwidth is already below those 20 kHz, how can the overall loop bandwidth be 20 kHz??

Since KD and Kvco determine the natural frequency, both parameters also influence the BW of the loop.

Influence yes, but what I've read so far KD and Kvco both act as a lowpass, so they can only decrease the overall bandwidth of the loop - and not increase it. In other words: The overall loop bandwidth is always smaller than the filter bandwidth: BW_loop > BW_filter
If I now want a loop bandwidth of let's say 20 kHz, I've got to choose the filter bandwidth somewhere above 20 kHz.

Did I misunderstand something there?

A PLL is a control loop where an error signal is fed back to influence the VCO. In the theory of control loops the loop gain is a critical factor. The loop gain is the gain the signal experiences passing once around hte loop. In a PLL as you have drawn it is

G(s) = KvKd F(s) / (sN)

where F(s) is the loop filter and N the division ratio.

The only frequency dependence is in F(s)/s

The loop bandwidth is where |G(jw)| = 1

Increasing Kv or Kd will increase the bandwidth.

You are using ADI devices, have you tried ADIsimPLL, this software package (free from ADI) designs the loop filter, allows you to alter the bandwidth, phase margin etc and see the effect on the loop gain, transient response, phase noise etc.

 

[biff44]

increasing bandwidth pll vco

You are confusing two concepts. The loop filter contains control loop "poles" and "zeros".

The total control loop has an open loop bandwidth, where its open loop gain equals 1.

They are not the same at all. They are related somewhat, but only in a complex way.

To understand this concept, you might want to try a simple exercise. Select a loop filter with a single pole frequency and a single zero frequency. Lets say the pole frequency is 20 KHz, and the zero frequency is 50 KHz.

Now plot the open loop gain and phase on a bode plot for your loop. To do this you will need to know the phase detector gain, VCO tuning gain, and the divisor ratio. For this exercise, assume these are all just constants.

Do the bode plot. Now notice where the open loop gain crosses the 0 dB line. That is your open loop bandwidth. Also notice at that same frequency, what is the open loop phase shift.

Now add a +10 dB gain stage after the loop filter, with flat constant gain. Replot the bode plot. What is the new Open Loop bandwidth? Why is it much bigger now--you did not change the loop filter component values at all? What is the new open loop phase shift?

Rich

 

[LvW]

vco bode plot

..............
The total control loop has an open loop bandwidth, where its open loop gain equals 1.
.............

I suppose, there is typing error as it should be "closed loop bandwidth" instead of "open loop bandwidth" .

 

[biff44]

questions of pll

I guess I would agree. The closed loop bandwidth is where the open loop gain crosses unity.

 

[arefeidi]

vco loop bw plot

Thanks to all three of you, that really helped me alot. So the loop bandwidth has nothing to do with a 3-dB-bandwidth - I think that's where my confusion came from.

I think I'm getting the principle now:
a) I've got the transfer function F(s) of my filter
b) Kvco and Kd are working like "offsets" for the bode plot of F(s)
c) The point where the resulting bode plot (open loop) crosses 0dB is my loop bandwidth
d) So when I now increase the charge pump current I shift the whole open loop bode plot a few dB up - resulting in an increasing bandwidth

 

[biff44]

loop bandwidth pll zero crossing

Precisely. The open loop gain slope is 20 db/decade of most PLLs in the vicinity of the 0dB crossing. So if you increase the gain, the whole open loop gain curve goes up. Because of that, the open loop gain now crosses the 0 dB gain line at a higher frequency.

You do, of course, have to be careful of phase too. If you just increase or decrease the gain to get the desired bandwidth, you may not have sufficient phase margin to keep the loop stable.

 

[arefeidi]

determine vco gain

Great to see some of the question marks disappearing in my head - thanks for your help!

 

[biff44]

loop gain vco

When I am soldering on new capacitor values on a PLL, this is the picture I have in my head:

The solid black curve shows the starting point open loop gain of a simple PLL (by simple I mean only one loop filter pole and one zero). The open loop gain is crossing 0 dB at 10 KHz, so I would expect my closed loop bandwidth to be around 10 KHz also.

Note that there is a zero at 1 KHz. Also note that there is plenty of phase margin at the frequency where the o.l. gain crosses 0 dB.

Now, if I screwed around with the gain, but did not change the pole or zero frequency (added a linear 20 dB gain op amp just before the oscillator), I would now have the open loop gain plot shown in red. Note that the closed loop bandwidth is now much bigger (around 100 KHz).

Now if I removed that additional op amp stage, and instead replaced it with a 20 dB loss (resistive attenuator). I would have reduced the orignal solid black lines gain by 20 dB, and the dashed black line would result. Note that the closed loop bandwidth is not much smaller (around 1 KHz). Also note that I do not have much phase margin any more (only 45 degrees), so the loop will like to ring. I would also expect a phase noise bump around 1 KHz.

Keep this picture in your head, and it all starts to make some sense.

You want to stay away from -180 degrees of open loop phase at the frequency where the open loop gain crosses 0 dB. That is because you want a stable loop. If the control loop forward gain is G(s), and the feedback gain is H(s), you can find in any basic control loop theory book that the closed loop transfer function is T=G(s)/(1 + G(s)H(s)). If |G(s)H(s)|=1, and ang [G(s)H(s)]=-180 degrees, then the T=G(s)/(1 - 1)= infinity at that one frequency. That is how you make a control loop oscillate. Even if you are only close to -180 degrees, you will see that the transfer function gain peaks way up, and that is why you sometimes see phase noise peaking at the loop bandwidth frequency.

Rich

 

[arefeidi]

pll open loop bandwidth

Thanks again for your explanations, especially the part about stability. Now as I have the basics I'll "just" have to build up the whole thing and get it to work