A Fast Locking All-Digital Phase-Locked Loop via feed forward compensation technique

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guys can anyone help me to design this.

Pick one:
- deity of your choice
- you

Just pick whatever works for you and gets the job done.

Bonus help: if you expect people to help, at least take the time to write up a proper non-ambiguous list of requirements.
 

I suggest you start reading a verilog or VHDL tutorial. you chose.
 

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