Josephchiang
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Does the digital circuit which without reset signal exist?
if it don't, it mean the "power on reset circuit" is needed in each digital circuit.
The difficulty to implement the power on reset circuit on my chip is that the reset time interval is a very long time (Max. about 1 second) as shown in the figure.
So it need a very large value of Resistor and Capacitor to achieve this goal.
But it is not practicable in the fully on chip design.
Any suggestion is helpful,
Thanks in advance.
Best regards,
Joseph
if it don't, it mean the "power on reset circuit" is needed in each digital circuit.
The difficulty to implement the power on reset circuit on my chip is that the reset time interval is a very long time (Max. about 1 second) as shown in the figure.
So it need a very large value of Resistor and Capacitor to achieve this goal.
But it is not practicable in the fully on chip design.
Any suggestion is helpful,
Thanks in advance.
Best regards,
Joseph