8bitchecksum using one adder

[nvm]

I am trying to implement 8bit checksum using just one adder. I am trying to use for loop but having trouble naming my variables in a way that could be used in the loop. I don't have any ideas on how to go by it for now. So I am open for all suggestions. The code for now looks like this:

 library IEEE;

use IEEE.std_logic_1164.all;

entity checksum8bit is
port (
  	serialnumber : in std_logic_vector (31 downto 0);
	countervalue : in std_logic_vector(15 downto 0);
	Finalsum : out std_logic_vector (7 downto 0)
);
end checksum8bit;


architecture behavioral  of checksum8bit is
   -- signal, component etc. declarations


component checksum
	port( DataA : in    std_logic_vector(7 downto 0);
          DataB : in    std_logic_vector(7 downto 0);
          Sum   : out   std_logic_vector(7 downto 0)
        );
end component;


BEGIN

process 

VARIABLE SUM1 : STD_LOGIC_VECTOR (7 DOWNTO 0) := "00000000";
VARIABLE DATAPAC(1)  : STD_LOGIC_VECTOR (7 DOWNTO 0) := SERIALNUMBER(31 DOWNTO 24);
VARIABLE DATAPAC(2)  : STD_LOGIC_VECTOR (7 DOWNTO 0):= SERIALNUMBER(23 DOWNTO 16);
VARIABLE DATAPAC(3)  : STD_LOGIC_VECTOR (7 DOWNTO 0):= SERIALNUMBER(15 DOWNTO 8);
VARIABLE DATAPAC(4)  : STD_LOGIC_VECTOR (7 DOWNTO 0) := SERIALNUMBER (7 DOWNTO 0);
VARIABLE DATAPAC(5)   : STD_LOGIC_VECTOR (7 DOWNTO 0):= COUNTERVALUE(15 DOWNTO 8);
VARIABLE DATAPAC(6)   : STD_LOGIC_VECTOR (7 DOWNTO 0):= COUNTERVALUE (7 DOWNTO 0);
begin
for I in 1 to 6 loop
checksum_1: checksum port map (
	DataA => sum1
	DataB => DATAPAC(1),
	sum => sum1
end loop;
end process;


Finalsum <= sum1;

end behavioral ;

Thank you.

 

[TrickyDicky]

you cannot instantiate a component inside a process, and also you cannot map a variable to a port map. And using a for loop just elaborates to parralel hardware, so you would actually have used 6 adders.

 

[nvm]

Okay. You have any other suggestions on how can I implement it using the least amount of gates?

you cannot instantiate a component inside a process, and also you cannot map a variable to a port map. And using a for loop just elaborates to parralel hardware, so you would actually have used 6 adders.

 

[ads-ee]

Okay. You have any other suggestions on how can I implement it using the least amount of gates?

If you can tolerate latency in the checksum calculation, you can share the one adder by using an FSM to control the checksum computation. The latency you will incur is directly proportional to the number of adds required to compute the checksum.

Regards