800MHz Power Amplifier Design Process

The process is partially correct. But No.4 is not true.
Power Transistors have Optimum Load Impedances that maximize either Delivered Power or PAE or Power Gain.
These three specifications cannot be maintained simultaneously and those Optimum Impedances are either given by manufacturer's Measurements ( Page 7 in Datasheet) or Simulated with accurate models. Measurements are generally correct.
These Impedances ( Source and Load ) must be matched to 50 Ohm, not Output/Input Impedances of the Transistor.

Layout is another story.

Look at also Ampleon that still manufactures a wide range of RF Power Transitors ( former NXP components )
There are many application notes and reference designs on their website. You can find easily an appropriate one.

Also look at
www.wolfspeed.com

Hi Big Boss,

Thank you for sharing and confirming the process.
In continuation to the 800MHz PA design; I have some more questions as below.
1. By using AWR to plot transfer character; I am confused to as where I should consider the saturation point starting from? Does marker 1 be considered as a good pointView attachment 178130
View attachment 178131



2. I plotted the IV using the below schematic and got the IV curve with further image.
Since I want a class A operation bias point for the PA; where should the Marker be located at?
Also, from the datasheet(https://www.nxp.com/docs/en/data-sheet/AFT09MS015N.pdf) ; I wanted to use the Table 8 specification which is VDD 12.5DC; IDQ = 100mA. But how do I obtain that plot/marker in AWR? Marker 2 is the closest I can get to 100mA. How can i get 100mA exactly?





3. The next step I did was stability circles.
The first image is without any series stabilization resistor adn the second image is the stability circle for the first circuit





I was able to stabilize the circuit by adding a series resistor to the transistor. But when I do so, the stabilization is good but the S21 drops from apprx 19dB(along with matching network) to 13dB. Is there a way to increase it? Like a different stabilization techniques?

4. Then I did input matching. The circuit is below. After designing the input matching network, the smith chart was close to 50Ohms at870MHz. I have not matching the output as of now. But the question is, from datasheet figure 8; where do I use the zsource/load information?




5. Similarly, I did from output matching as well and got the smith cart to 50 Ohms at 870MHz.
6. The final s values are shown in the below image. the schematics is following it. The question is, is this a good amount of gain and good loss?




Thanks all for advising me.

Your attachments 178130 & 178131 do not appear. Try re-posting them.

The best is to use in your simulation input and output LTUNERs. And when the tuning is done, replace the tuners with LC components (a simple low-pass LC matching network should work).
I found on the net this basic example of a 30W 450MHz LDMOS power amplifier.
The transistor MRF9030 works up to 1GHz so you can try using it at 800MHz.
To verify further the linearity of the PA (for class-A) may need to run a two-tone test and check the IMD (have to add at the input, via a combiner, two RF power sources, about 100kHz spacing). As is mentioned in the MRF9030 datasheet.

LTUNER is not necessary to analyze a simple IV Curves. BIASTEE component is sufficient.

Then you should squeeze the V_GS voltage to obtain the right value.

The first step to verify the fundamental parameters by drawing a test set-up. You can enter Optimum Load and Source Impedances directly into Port elements






There are possibilities of discrepancy between measured data and model data. It's normal.
Now compare these results with datasheets' measured data.
I attach the project archive file you to inspire.

BigBoss said:

LTUNER is not necessary to analyze a simple IV Curves. BIASTEE component is sufficient.
View attachment 178152
Then you should squeeze the V_GS voltage to obtain the right value.
View attachment 178148
The first step to verify the fundamental parameters by drawing a test set-up. You can enter Optimum Load and Source Impedances directly into Port elements
View attachment 178153
View attachment 178154
View attachment 178155
View attachment 178156


There are possibilities of discrepancy between measured data and model data. It's normal.
Now compare these results with datasheets' measured data.
I attach the project archive file you to inspire.

Click to expand...

Hi Big Boss,

Thank you for sharing the AWR file. It was extremely helpful for a starter like myself.
I continued with the design and and had some more questions as below.



1. I plotted the Mu factor. My question is,
1.1] Do I plot the mu factor with only the bias network and no matching network?
1.2] My factor was above 1 from 760 to 870 MHz similar to that of the datasheet's design. But I wanted the mu factor to be above 1 from 500MHz to nearly 1GHz. So I added a series resistor. By doing so; the mu factor was above 1(not shown below) but when I plotted the input v output power graph, I got extremely low output power. So, how can I stabilize the FET beyond frequency of operation and still obtain good inputVouput power?




2.
I design an input matching network as shown below with the smith chart results. Port 2 is the Z source from the datasheet. From the smith chart, the matching looks good; is this correct?




3.
Similarly; I designed the output matching as well and the smith chart results. Again; I believe this is a good matching, right?





4. From my understanding; now, since, the input and output have been matched to 50 ohms with their respective source and load impedance from the datasheet.
So, I plotted the input power v output power graph again as shown below for the below circuit (the impedance is also written for clarification).
From the design file Big boss provided; I required 17.35dBm input to get 6W output. This was withOUT any input/output matching. And this was good. However, after performing the matching; the input requirement is now 26.76 dBm for 6W output. This increase in input power requirement, is it normal because of matching losses or did I do something wrong?


No matching

below is with matching





5. What are the next steps to be followed for me to continue the design? I know the layout comes next; but is there something else that I should take care of before moving to layout?

I have attached my AWR file; just in case you wanted to have a look at it. Unfortunately, it is not very pretty and clean!!

Thanks for your advise,

First observation.
The Port Impedances must be complex conjugate of the Optimum Load/Source Impedances. If the transistor wants to see an impedance at both Input and Output, the Source Impedance(s) must have complex conjugate with Matching Circuit. Like that;

If you design the matching circuit carefully, you can obtain good results.


Consider Microstip Lines instead Inductances for Matching Circuits because low valued Inductances have bad tolerances.
View attachment 1661502486537.png

Hi Big Boss,

Thank you for sharing about the input/matching network.
That was the main cause for why I did not get good results.

>> I improved the input and output matching and was able to obtain 6Ws at 18dBm input, which is similar to its datasheet.



>> I was wondering if you can share some insights to the stability question in the previous thread. I am still a confused in this aspect.

>>Regarding S parameter plots; I get the below results. The S21 seems to be great; but the S11 and S22 is not that great. Any idea why this might be the case even though I get 6W at 18dBm input(same as datasheet) and the input/output is matched .


>> Lastly, moving forward, I was wondering; what shall be the next steps other than converting the input/output network to microstrips.

Thanks for your advise.
Mahruz

Don't worry about S11 and S22 because you have done Power Matching not Conjugate Matching.
This is normal for Power Amplifier because Small Signal Input and Output Impedances are completely different than Large Signal Optimum Load and Source Impedances.
In order to see where the "conditional instability" comes from, you check both Input and Output Stability Circles and then you place parallel resistance to push out the problem circle(s).
Don't insert series resistance because Impedances are very low and the amplifier will fall.

Hi All,
In continuation to above thread; I designed the matching networks for 870Mhz and it is very good.
However, I wanted almost similar output(above 6W) from 849Mhz to 870MHz.
So, I redesigned the matching to 860Mhz as it is the central frequency for the band I am looking for.
But as you can see, in the image below, after the mactching is done; at 849 and 870Mhz; there is very low power.
How can I make the design work for 849 to 870 MHz with at least 6W for the full band?





Thanks for your advise.
Mahruz

Seeing the high peak at center, it seems you have high Q (goes hand-in-hand with high selectivity).

Q is influenced by L:C ratio. Try reducing this by reducing L values and raising C values, a little bit at a time.

BradtheRad said:

Seeing the high peak at center, it seems you have high Q (goes hand-in-hand with high selectivity).

Q is influenced by L:C ratio. Try reducing this by reducing L values and raising C values, a little bit at a time.

Click to expand...

Hi BradtheRad,
Thanks for sharing that. I was able to change it and it was successful.

Hi All,
I was trying to convert the input matching network from lumped element as shown below(first image) to microstrip(third Image) with same performance(second image) but not sure on how to do so in AWR.
Not sure if I should use TLIN or MLIN or something else?
Please help.








Thanks,
Mahruz