8 Bit ALU Verilog Code

[forast]

I have a very difficult time understanding verilog and programming on it. Is there anyone that can help me with 8 bit ALU Module code or at least how to understand this better? We're also suppose to design a 8 bit 4 to 1 mux and 8 bit 2 to 1 mux. I think I figured out the 2 to 1 mux but what I'm not sure if I'm understanding is that these are separate files? So the ALU Module is separate from the 2 to 1 mux module? Then later on in a test bench i'll use all the files to appropriately get the right output?

 

[mrflibble]

There are a lot of people the past month that have a very difficult time understanding verilog and programming and also have to do an ALU homework assignment. You can use the search function to find the relevant posts.

 

[forast]

Hmm I looked at it, still confused. I understand a little bit of it but nothing enough to be confident on my own. I don't understand why verilog is so difficult or if the class just is going too fast. I didn't even know what verilog was or how it worked a month ago.

 

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Do you have any idea what a mulitplexer is? Do you know what the truth table of a multiplexer looks like? Can you convert a truth table to a boolean expression? If not then you've got more of a problem understanding hardware and logic design than a problem with Verilog.

Verilog isn't "hard" it's just a way to represent hardware using text. It might be hard if you don't understand what the underlying hardware does.

You might want to invest in a book like this: https://www.amazon.com/Hdl-Chip-Design-Synthesizing-Simulating/dp/0965193438 It shows the synthesized logic for the RTL code for both VHDL and Verilog.

regards

 

[forast]

Do you have any idea what a mulitplexer is? Do you know what the truth table of a multiplexer looks like? Can you convert a truth table to a boolean expression? If not then you've got more of a problem understanding hardware and logic design than a problem with Verilog.

Verilog isn't "hard" it's just a way to represent hardware using text. It might be hard if you don't understand what the underlying hardware does.

You might want to invest in a book like this: https://www.amazon.com/Hdl-Chip-Design-Synthesizing-Simulating/dp/0965193438 It shows the synthesized logic for the RTL code for both VHDL and Verilog.

regards

Maybe that's what I need to focus on then. I do know what a multiplexer is and I do understand and know how the table of a MUX looks like somewhat. I can do truth tables to boolean expressions. If all you're saying is I need to just understand the language and convert the design into verilog then maybe I'll focus on understanding the concept a little more fully.

 

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The majority of learning how to code in Verilog is just learning what the synthesis tools will do with your code and what the resulting circuit looks like. That is why there are suggested methods of writing Verilog/VHDL to represent various logic blocks like: registers, mulitplexers, selectors, etc.

https://asic-world.com/examples/verilog/index.html
has a bunch of examples of writing various constructs in Verilog.

Regards

 

[forast]

The majority of learning how to code in Verilog is just learning what the synthesis tools will do with your code and what the resulting circuit looks like. That is why there are suggested methods of writing Verilog/VHDL to represent various logic blocks like: registers, mulitplexers, selectors, etc.

https://asic-world.com/examples/verilog/index.html
has a bunch of examples of writing various constructs in Verilog.

Regards

Lets say in this particular example where there's an ALU Module and there's a 4-1 MUX with some ADD, SUBTRACT, XOR, AND gates or stages(not sure if I'm using the correct term.) When I program this I will need to code a 4-1 MUX Module in it's own file, the XOR on it's own file, the ALU Module on it's own then a test bench correct? So setting this up correctly will require numerous files. Then i'll instantiate the ADD, SUBTRACT, etc. in the 4-1 MUX and it should put the correct output? Thanks for the help btw, this is the only place that I could find that is very helpful with verilogs.

 

[pbernardi]

No, you can add all the operations in the same file. Let´s say:

module ALU (
  input        [1:0] OP ,
  input              CLK,
  input        [7:0] A,
  input        [7:0] B,
  output reg   [7:0] OUT
);

wire [7:0] MUX [0:3];

assign MUX[0] = A + B;
assign MUX[1] = A - B;
assign MUX[2] = A ^ B;
assign MUX[3] = A & B;

always@(posedge CLK)
begin
  OUT <= MUX[OP]
end

I made the code withou testing (I have no ISE in this machine), but it should work.

But you *can* use several independent operations to make a bigger component, it is up to you. When to use a bigger component or when use several small modules? I suggest thinking in ICs. For example, If you think you should have one IC for add, one IC for sub, etc., you should use several small modules. If you think you can make an IC with add, sub, xor, and, then you should make one single module. Got it?

Also, you can add the test bench in the same file as well. You just have to be sure to assign the correct module as top level (not the simulation module)

 

[forast]

No, you can add all the operations in the same file. Let´s say:

module ALU (
  input        [1:0] OP ,
  input              CLK,
  input        [7:0] A,
  input        [7:0] B,
  output reg   [7:0] OUT
);

wire [7:0] MUX [0:3];

assign MUX[0] = A + B;
assign MUX[1] = A - B;
assign MUX[2] = A ^ B;
assign MUX[3] = A & B;

always@(posedge CLK)
begin
  OUT <= MUX[OP]
end

I made the code withou testing (I have no ISE in this machine), but it should work.

But you *can* use several independent operations to make a bigger component, it is up to you. When to use a bigger component or when use several small modules? I suggest thinking in ICs. For example, If you think you should have one IC for add, one IC for sub, etc., you should use several small modules. If you think you can make an IC with add, sub, xor, and, then you should make one single module. Got it?

Also, you can add the test bench in the same file as well. You just have to be sure to assign the correct module as top level (not the simulation module)

Thanks I will take a look at that within the next few days, gotta finish a project for my other class. I'm sorta understanding it more now. I'm gonna try to understand it more as someone said if I understood the concept and how they work then coding it should be fairly easy so I'll do that. I'll report back if I have any issues.