8 Bit adder/Subtractor using verilog on active HDL

[Graci]

I am designing a * bit adder/subtractor..code is given below, somehow m not getting the correct output and m not able to find out the problem.
Can anyone look into the code and suggest corrections?

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
module fa_1 (cin,a,b,sum,carry);
    input cin,a,b;
    output sum,carry;                    
    assign sum = a^b^cin;
    assign carry = (a&b)|(b&cin)|(cin&a);
    //wire x,y,z;
    //xor i_xor (x,a,b);
    //and j_and (y,x,cin);
    //and k_and (z,a,b);
    //or l_or (co,y,z);
    //xor m_xor (sum,x,cin);
endmodule
 
    module addSub_x8 (a,b,addSubtract,sum,carry);
    input wire [8:1] a,b;
    input wire addSubtract;    
    output [8:1] sum;
    wire [7:1] co;
    output carry;
    wire [8:1] s;
    xor(s[1], addsubtract ,b[1]);
xor(s[2], addsubtract ,b[2]);
xor(s[3], addsubtract ,b[3]);
xor(s[4], addsubtract ,b[4]);
xor(s[5], addsubtract ,b[5]);
xor(s[6], addsubtract ,b[6]);
xor(s[7], addsubtract ,b[7]);
xor(s[8], addsubtract ,b[8]);
    
    fa_1 t1 (co[1],sum[1],a[1],s[1],addSubtract);   
    fa_1 t2 (co[2],sum[2],a[2],s[2],co[1]);
    fa_1 t3 (co[3],sum[3],a[3],s[3],co[2]);
    fa_1 t4 (co[4],sum[4],a[4],s[4],co[3]);
    fa_1 t5 (co[5],sum[5],a[5],s[5],co[4]);
    fa_1 t6 (co[6],sum[6],a[6],s[6],co[5]);
    fa_1 t7 (co[7],sum[7],a[7],s[7],co[6]);
    fa_1 t8 (carry,sum[8],a[8],s[8],co[7]);
endmodule

---

 

[TrickyDicky]

I suggest yo write a testbench and try and debug it yourself in a simulator.