Correct.Interesting how the Philips datasheet shows completely different signal names to the On-semi one. At least the pin numbers match up.
Just to be clear - pin 9 of the first chip goes to pin 14 of the next?
I measure 8 rising edges , I don't understand what you mean by 7.5 clocks
@alexan_e Are you sure that there is a problem here?The cause of the error is that you provide the data synchronized on falling edges while the shift register operates on rising edges.
I agree that it does not matter if data is changed at some time other than falling edge, but surely it is vital that data does NOT change exactly on a rising edge, which is what the green scope trace does.I don't see a point of entering the data on falling edge, as you have already noticed the data in the output to the second chip (and the rest) will be on rising edge so you can't keep that falling edge timing.
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The shift register works on rising edges, this will not change because you want to enter data on falling edges.
Both input and output process data on rising edge.
If the scope traces are an accurate representation of the signals on the 74HC595 pins, then there seems to be something badly wrong.
If the input of the first chip changes on falling clock (so it is stable on a rising clock), then the input to the second chip should change on a falling clock.
The green trace (if accurate) is the source of the second chip's data input, so I would think it should change on falling clock - but it does NOT.
Hey, I finally get it! Thank you very much.What I'm trying to say is that what you describe can't happen, no matter what you do the output to the second chip will be synchronous data on the rising edge, that is what the manufacturer has designed and that is what the second chip will get and then give to the third, you can't add delay to the clock after each chip in order to provide an input state before the edge.
The frequency is 250kHz.Your clock frequency is about 250KHz ?
Maybe you get the wrong data becasue you are entering data on falling edges, can you use rising edge logic?
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