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1. go through .cdl file and find the pin order in the subckt and put that info into associative arrays with cell names as keywords.
2. Parse the verilog netlist ,and find a cell name and pin names,and net names connected to each pins.
3. Put the cell name into the associative array from #1, and associate the pin order in subckt with net names from #2.
4. Add 'X' to the instance name and print it as well as net connetion info and cell name from #3.
5. Go to #2.
I am still confused. I am stuck at this point since a few weeks and want to move ahead. I have verilog file and I need TRANSISTOR level spice netlist. how do I get it? I do not know Perl.
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