Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

perl code which converts verilog flat netlist to spice netli

Status
Not open for further replies.

pd

Full Member level 1
Joined
May 23, 2006
Messages
99
Helped
5
Reputation
10
Reaction score
3
Trophy points
1,288
Location
India
Activity points
2,243
perl hspice

Hi,
I require a perl code which converts verilog flat netlist to spice netlist .Can anybody help me in that?


Thanks,
 

Re: perl code which converts verilog flat netlist to spice n

Hi

First put a sample verilog code here.


tnx
 

Hi jim,

Even I want to know...so restarting the thread

module c432 (N1,N4,N8,N11,N14,N17,N21,N24,N27,N30,
N34,N37,N40,N43,N47,N50,N53,N56,N60,N63,
N66,N69,N73,N76,N79,N82,N86,N89,N92,N95,
N99,N102,N105,N108,N112,N115,N223,N329,N370,N421,
N430,N431,N432);

input N1,N4,N8,N11,N14,N17,N21,N24,N27,N30,
N34,N37,N40,N43,N47,N50,N53,N56,N60,N63,
N66,N69,N73,N76,N79,N82,N86,N89,N92,N95,
N99,N102,N105,N108,N112,N115;

output N223,N329,N370,N421,N430,N431,N432;

wire N118,N119,N122,N123,N126,N127,N130,N131,N134,N135,
N138,N139,N142,N143,N146,N147,N150,N151,N154,N157,
N158,N159,N162,N165,N168,N171,N174,N177,N180,N183,
N184,N185,N186,N187,N188,N189,N190,N191,N192,N193,
N194,N195,N196,N197,N198,N199,N203,N213,N224,N227,
N230,N233,N236,N239,N242,N243,N246,N247,N250,N251,
N254,N255,N256,N257,N258,N259,N260,N263,N264,N267,
N270,N273,N276,N279,N282,N285,N288,N289,N290,N291,
N292,N293,N294,N295,N296,N300,N301,N302,N303,N304,
N305,N306,N307,N308,N309,N319,N330,N331,N332,N333,
N334,N335,N336,N337,N338,N339,N340,N341,N342,N343,
N344,N345,N346,N347,N348,N349,N350,N351,N352,N353,
N354,N355,N356,N357,N360,N371,N372,N373,N374,N375,
N376,N377,N378,N379,N380,N381,N386,N393,N399,N404,
N407,N411,N414,N415,N416,N417,N418,N419,N420,N422,
N425,N428,N429;

inv_1 U36 ( .Z(N118), .A(N1) );
inv_1 U37 ( .Z(N119), .A(N4) );
inv_1 U38 ( .Z(N122), .A(N11) );
inv_1 U39 ( .Z(N123), .A(N17) );
inv_1 U40 ( .Z(N126), .A(N24) );
inv_1 U41 ( .Z(N127), .A(N30) );
inv_1 U42 ( .Z(N130), .A(N37) );
....................
...................
 
Last edited:

1. go through .cdl file and find the pin order in the subckt and put that info into associative arrays with cell names as keywords.
2. Parse the verilog netlist ,and find a cell name and pin names,and net names connected to each pins.
3. Put the cell name into the associative array from #1, and associate the pin order in subckt with net names from #2.
4. Add 'X' to the instance name and print it as well as net connetion info and cell name from #3.
5. Go to #2.

it's not very hard if the netlist is flat.
 
@lostinxlation and @Pavan,

I am still confused. I am stuck at this point since a few weeks and want to move ahead. I have verilog file and I need TRANSISTOR level spice netlist. how do I get it? I do not know Perl.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top