Number of gates used depends on circuit which you r implementing , such as inverter will have basic 2 cmos gates , whereas NOR , NAND will have minimum of four cmos gates . But , you can divide each NMOS gates in NAND depending on your need , after diving you will get 2 PMOS + 4 NMOS = 6 CMOS gates . Same in case of NOR , where you can divide PMOS gates , reaulting in 4PMOS + 2 NMOS = 6 cmos gates .
This is generally related to height of stack . logical functionality remains same.