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6 layer stack-up recommendations

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Jester

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I'm looking for stack up recommendations (keeping in mind readily available materials) for a 6 layer board I'm working on.

Design requirements dictate the following:

- maximum 6 layers
- lots of high speed traces DDR3, SERDES, Gbit ETH, USB2.0 etc
- high speed signals due to BGA need to be 4mils wide

So for 50/100Ohm with 4mil traces, the two inner signal layers need to be close to the ground and VCC planes (about 6 mils), this results in a total stack up of only 35mils assuming 4.3mil outer cores and 8 mil center core. So either I have a "thin" PCB at 35 mils or increase the center core to 35 mils or so and that will hurt the inter-plane capacitance.

So is a less than nominal 63 mil board a bad idea (perhaps to much board flex?) or do the advantages of more inter-plane capacitance outweigh a thin board?

Any 50 Ohm, 4 mil trace, 6 layer stack up suggestions are welcome
 

marce

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Re: 6 layer stackup 4mil trace

Is this a PC based design with a south and north bridge chips?
How many positive supplies do you have?
BGA pin pitch, size, number of pins?
Board size, mounting hole positions?
End use and environmental factors?
 

Jester

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Re: 6 layer stackup 4mil trace

Is this a PC based design with a south and north bridge chips?
How many positive supplies do you have? 4: +5V(pwr in), 3.3V, 1.5V(DDR), 1.0V (Core)
BGA pin pitch, size, number of pins? 689(1mm), 256(1mm), 96(0.8mm)
Board size, mounting hole positions? ~6" x 6", non standard holes
End use and environmental factors?

Is this a PC based design with a south and north bridge chips? No this is a processor board for an industrial related product using a dual core QorIQ (P1020)
How many positive supplies do you have? 4: +5V(pwr in), 3.3V, 1.5V(DDR), 1.0V (Core)
BGA pin pitch, size, number of pins? 689(1mm), 256(1mm), 4x96(0.8mm)
Board size, mounting hole positions? ~6" x 6", non standard holes
End use and environmental factors? Industrial -40 to +70
 

Jester

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Re: 6 layer stackup 4mil trace

I would suggest without looking at the schematic that 8 layers may be better. I will do some more research and be back.

For a start here is a good reference:
http://www.pa.msu.edu/hep/atlas/l1c...ntorpaper_bga_breakouts_and_routing_52590.pdf

I agree on the 8 layer however one of the design criteria is "PCB to be 6 layers maximum". I'm 99% complete on the layout, will perform simulation in the next day or so with this stackup* and see how it looks.

*
1/2 oz -Top
2 x 106
1/2 oz - GND
6mil core
1/2 oz - signal
2 x 2116
1/2 oz - signal
6mil core
1/2 oz - VCC
2 x 106
1/2 oz - Bottom

Overall thickness = 35mil
 

marce

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Re: 6 layer stackup 4mil trace

Good luck, have you got signals crossing splits in the power layers?
 

Jester

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Re: 6 layer stackup 4mil trace

No, solid plane for gnd (entire board), I split the 3v3 plane as it is not used in DDR area, so I use that plane for power in DDR area
 

andre_teprom

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Re: 6 layer stackup 4mil trace

In order to avoid possible cross-interference between neighbors signals, it is very important that routing in the adjacent layers are alternately mutually orthogonal one each to another, as follows:

  • Mounting TOP ( Vertical )
  • GND
  • signal ( Horizontal )
*** [ SUBSTRATE ]
  • signal ( Vertical )
  • VCC
  • Mounting BOTTOM ( Horizontal )





+++
 

Jester

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Re: 6 layer stackup 4mil trace

In order to avoid possible cross-interference between neighbors signals, it is very important that routing in the adjacent layers are alternately mutually orthogonal one each to another, as follows:

  • Mounting TOP ( Vertical )
  • GND
  • signal ( Horizontal )
*** [ SUBSTRATE ]
  • signal ( Vertical )
  • VCC
  • Mounting BOTTOM ( Horizontal )

+++

I have avoided parallel traces on the (vertical) signal layer.

Thanks for your comments.
 

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