5V single supply ±20V input， how to design the ESD IO

[houjiali]

My chip is a single suppy with 5V and 0V ground.

But sometimes the input signal is up to ±20V，the tranditonal GGNMOS ESD will suffer big leakage (body to drain).

Is there any ESD architecture to meet this spec?

Thanks

 

[KlausST]

Hi,

Some ICs can withstand this.

But we don't know which IC you use, thus we can not give any dedicated answer.

First look into the datasheet about the max. allowed Input voltage.
Then you have to decide what to do.
Maybe nothing, maybe a voltage limiter, maybe a resistive divider, ...

Btw: ESD voltage is usually not in the range of +/-20V it's usually in the kilovolts range.

Klaus

 

[houjiali]

Sorry，I‘am designing this chip. The ESD voltage is 8kV. And the input voltage of the chip is ±20V. The problem is when the input voltage is higher than 5V or lower than 0V. The tranditional ESD circuit will clamp the voltage. so I need design a new ESD circuit to accept ±20V input voltage。

 

[houjiali]

View attachment 152266

My chip is a single suppy with 5V and 0V ground.

But sometimes the input signal is up to ±20V，the tranditonal GGNMOS ESD will suffer big leakage (body to drain).

Is there any ESD architecture to meet this spec?

Thanks

I'am designing this chip. If the tranditional GGNMOS is used. When the input voltage is higher than 5V or lower than 0V, the input signal(±20V) will be clamped.