50V GaN device Bias Sequencing Card

[rajan_pec]

Hi,

I need to have Bias Sequence card for GaN based Power Amplifier.

GaN based device needs sequencing , Gate voltage (-5V to -2V) first and then Drain voltage (Vd) (28 to 50V).
I have followed the app note (attached here) for my requirement. I have placed N-Channel MOSFET (PSMN8R2-80YS) in the final schematic.

I am getting +5V and -4V output but I am not getting Vd on the S-terminal of the MOSFET.
I am doubting on the Rsense Value. 10ohm (r24) Is it Correct?

Kindly help me in understanding this switching operation in LT4256 IC.:shock:

REgards,
Rajan

 

[mtwieg]

I don't see anything wrong with the schematic in the document. What voltage do you see on the UV and gate pins?

 

[dick_freebird]

I've done this function in integrated form for phased
array antenna element controllers and, if you do not
desperately need the lowest possible BOM cost, I
recommend you step away from the elaborateness
and use the PMOS load switch that they disparage.

Then your circuit could become extremely simple,
a NPN w/ B=GND, E through resistor to VG, C to the
high side loaded by a suitable shunt making -10V
for a -3V VG, and that node driving the PMOSFET
gate. You could get fancier with more gain and
sharper / more consistent VG thresholding, more
control of MOSFET gate drive and so on, if you
determined these had any value. But for dumb
simple gate-before-drain control you might get
away with really simple.

 

[mtwieg]

I agree that the circuit is pretty complex for just biasing a single device, and using Linear Tech components is pretty pricey as well...

 

[rajan_pec]

I don't see anything wrong with the schematic in the document. What voltage do you see on the UV and gate pins?

Thanks for the reply.

Board is working fine now. Earlier I was feeding +30V as Vcc which was not enough to provide more than +3.0V at UV pin.
After feeding +40V and resoldering the N-MOSFET & Zener Diode (BZX) , board is providing required Vd at the output.
Regards,
Rajan

- - - Updated - - -

I've done this function in integrated form for phased array antenna element controllers and, if you do not desperately need the lowest possible BOM cost, I recommend you step away from the elaborateness and use the PMOS load switch that they disparage. Then your circuit could become extremely simple,
a NPN w/ B=GND, E through resistor to VG, C to the high side loaded by a suitable shunt making -10V for a -3V VG, and that node driving the PMOSFET gate. You could get fancier with more gain and sharper / more consistent VG thresholding, more control of MOSFET gate drive and so on, if you determined these had any value. But for dumb
simple gate-before-drain control you might get away with really simple.

Could you explain this circuit in detail with a ckt diagram?
Regards,
Rajan

 

[rajan_pec]

Update: For initial testing , I have bypassed the temp compensation ckt. -4.6V Vout is taken out at connector through a three pin trimmer resistor (2K ohm). Thru this trimmer i am able to vary Vg from (-4.5V to -0.5V).
Vd (+48V) and Vg (-4.2V) signals switching timings are captured on CRO. Switching is correct with proper delay.

Problem: LAB Power Supply settings: V= +48V, Current limit = 1Amps
This board connected to GaN based RF PA card using good quality wires (Vd, Vg n GND). Powering On the board gives +48V and -3.8 V to RF PA card.
Using trimmer , Vg increased to -3.0 V (slowly) . As it reached -3.0V, PA device started drawing whole current (1Amps) and Vd drops to 0volt.
Why this is happening?

Note: Earlier I biased this RF PA card directly from a LAB power Supply & it was working fine . I took all RF measurments. For this RF PA, Id = 800mA @ Vg =-3.0V

Regards,
Rajan

 

[Andrew77]

if you look carefully the schematic you will notice a N-mos, instead You have to use a P-mos with the Source feed and the Drain towards the GaN..