Hi,
If you can run the complete PLL in closed loop mode, you can directly plot the phase noise of output clock. But it is difficult to run the simulation for the duration of lock.
If the simulation is done separately for different modules, below is what you can do:
It is random noise. Thus direct addition of noise of different blocks does not hold good. RMS addition should be done to get the proper result.
It can be done in three steps:
1) Convert db plots to normal plots
2) Do rms addition and get a resultant plot
3) Convert the resulting plot to dB again
Let me know if it solves the problem.