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[SOLVED] 50 Ohm resistance on a trasnmission line??? How can be this??? I don´t get it!

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Jan 22, 2014
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Hello guys,

I have to manage a a high speed clock of 150 MHZ and I am reading some documents about the termination resistance in high speed design and the most of them assuming that the line resistance is around 50ohm. I have measured my track with the multimeter and the resistance is around 1.5ohm!!!! Am I missing something??


Transmission line characteristic impedance isn't a resistance that can be measured with a multimeter. Although it behaves like a resistance under specific circumstances, it's never present at DC. See for a first idea.
ok I get it. So Can I assume that the Zo of a track and a flexible cable in a PCB is around 50 ohm right? On the other hand, if i want to increase the track impedance, how can i do it?? Connecting one resistance in parallel??? Thanks!

Z0 is set by the track geometry and substrate permittivity which changes the inductance and capacitance per length unit respectively. There are calculator for PCB transmission lines, e.g.

Adding resistors creates a lossy circuit and isn't the preferred way to change transmission line impedances, but sometimes necessary for impedance matching. What's your specific problem?

I have problem with the integrity of the clock signal. I need to drive a 150 Mhz clock generated by an FPGA placed in a "Main board" to a "Sensor board" trough a flexible cable...and measuring the signal with the Oscillscope I see a very nice square signal at the ouptut of the FPGA with the rigth low/high level (0-3.3), but however when I measure the same signal in the sensorboard, directly on the input of the buffer/driver, I see the same clock signal with an offset of 250 mv and its shape is like a sinus...I think that I have reflection problem because there is not any termination resistance in any PCBs (mainboard or sensorboard). So i have been thinking to use a thevenin termination close to the input driver/buffer in the sensorboard. But checking the FGPA characteristics (Cyclone IV) and assuming that the Zo is 50 ohm, I can't use any resistance value to be in compliance with the FPGA characteristics. So I need to set up a fixed value for Zo to estimate good values for the thevenin resistances...Anyway if you have other good idea about which termination resistance should I use for such as clock signal, I will be very grateful....Or maybe my problem is not a reflection problem....have you had this issue?

Thanks for your help!

Would be helpful if you can give a brief overview of the setup, cable and trace lengths, cable type and wire assignment (e.g. accompanying grounds).

You'll generally need some kind of signal termination, source series termination is often sufficient.

If the connection has some length (> 10-20 cm), I would prefer LVDS IO standard for the 150 MHz clock.

50Ohm coax it too high Capacitance. 100pF/m use 110 ohm Cat5 with pullup/down termination equivalent to 110 to 150 Ohm load and biased to 1.2~1.3 V or two Vbe drops.
If using dirty grounds, CM choke like those used for ethernet are needed. Signal swing needs only to be 1Vpp centred on 1.2 but no noise.

Thus use UTP cat 5 with 220 to gnd and 270 ohm to clean 3.3V and add CM choke around cable.

I am sorry for my delay. I am using the attache configuration. The flexible cable which I am using is this:

**broken link removed**

And there is one GND line between signal lines. The distance between the main board and the sensor board is 25cm and the lenght of the cable is 20cm. The FPGA I/O is configured like "3.3V-LVTTL" and reading some papers in internet they recommend to set up a R+C termination close to the buffer to avoid reflection and other no desired effects. However I am also afraid about the buffer. As you can see in the general overview of the system, the buffer that I am using is this one:

Do you think that it is going to be able to handle a 150MHz clock signal??? Becaus the datasheet speaks about Mbps and the maximum is 170Mpbs. So it means that it is able to handle freq <= 170MHz right???



And there is one GND line between signal lines.
That's only half the required information. You have a singled ended clock, so there can't be a ground between the clock signal lines anyway. But what are the wires next to the clock signal? How many ground lines do you carry in the 20-way cable?

As already said, I would prefer source side series termination over load parallel termination (e.g. with RC).

The impedance of a single ended line embedded by two ground lines in a 1/20" ribbon cable is around 60 to 70 ohms, if I remember right.

AWG28 on 1.27mm =0.05" centres will be around 100 ohm
Or 104 ohm....

All TTL like interfaces have a threshold of equiv of two transistor Vbe drops or 1.3V
Most CMOS buffers now are 50 ohm .. See specs for output and compute, Vol/Iol . Pls specify your PN.

Ideal match is 50 ohm series, 104 ohm termination to 1.3V with interleaved grounds or Thevenin equiv. as I outlined with pullup/down to 3.3V. Dielectric of PVC is 45pF/m so 0.2m is 90pF. No problem.

0.5V swing pp is minimal, 1Vpp is adequate around 1.3V.

@FvM: beside the 125MHz clock there SPI signals. But these SPI signals are only active in the sart up of the system to configure some registers. The rest of the time they are off..The rest of the wires are GND. Anyway I think that I should redesign the cable. So can you give some recomendation about what kind of cable should I use to drive this high speed clock? Furthemore how should be the signals beside the clock?

@SunnySkyguy: I am using a Cyclone IV EP4CE115 with the constraints 3.3LVTTL and maximum current. I can also enable the internal weak pull-up resistence. But I don't know if this is going to give me a better behavior...

Anyay I tried to put a source serial resintance of 330 ohm and the waveform looks much better than before. There is not any offset and I have the right voltage at the output of the buffer. However, I meausure the output and I can?t see any signal. So maybe the buffer is not enough faster to handle 150 MHz.the buffer that I am using is sn74avc8t245.


The sn74avc8t245 or AVC family came out around/before 2004 was based on old technology slight improved with 300-400 ESR at 3-3.6 V.
Input threshold is Vcc/2 therefore equal pull up/down is best at 300 Req. or 600to Vcc//600to gnd. But this still mismatches 104 Ohm transmission line so crosstalk is degraded plus tolerance mismatch on reflections.

Better choice for your signal integrity is 85 Ohm drivers using VHC family or 74VHC245xxx.

For future lower impedance striplines use ALVC2 family which is what ATMega uses.

Again look at delta Vo/delta Io for ESR to understand. If you need more transmission line theory, just look or ask.

probability of clocking error depends on SNR or symmetrical noise margins.

TTL is symmetrical power noise margin since driver was lowR for 0 and high R for 1 and threshold of 1.3 the floating input voltage.

now CMOS is backward compatible but more symmetrical now, so input mean threshold is V+/2.

do this to get best reliable clock in single ended, use differential for better SNR and low emissions or use ferrite busclamp.

I see. Ok I am going to use bus/buffer of the family 74LVXXX for example this one 74LVC126 (2014 technology). However haw can I figure out the max. operating frequency? In the datasheet there is only enabling times and propagation delays but there is no data for the max freq....

Thanks again...

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