... is wrong. D2 to Q3 of course. If you want a ring-shift: additionally D3 to Q0. You must initialize D3 (in case of shift left) by a log. "1" only for the first clock pulse: Connect Q0 via a 1kΩ resistor to D3, and D3 via a capacitor to VDD (1nF..1µF, depending on your clock frequency). S=HIGH for left-shift.