4 bit counter using 2 bits counters (vhdl)

hi,

i am new to the forum.
I was trying to understand how 2-bit synchronous counters
can be connected to form a 4-bit synchronous counter.
I have to implement this problem in strucutral VHDL.
Any help/guidance is needed.

thnks

The lower 2bits are just an output from a simple 2bit counter, and whenever the lower 2bit output becomes '11', increment the upper 2bits.

In the psuedo code, it should be like,
out_q[1:0]+1, and out_q[3:2]+1 are two 2bits incrementors. Besides two 2bit counters, you need multiplexers, comparators(XNOR cells), and flops.

thnks for the reply...
my requirement is to design the counter without use of flip-flops..
my vhdl code for 2 bit counter (behavioral model) is as follows..

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity two_bit_cntr is
port(clk : in std_logic;
reset : in std_logic;
count : out std_logic_vector(1 downto 0)
);

end two_bit_cntr;

architecture behvrl of two_bit_cntr is
signal c : std_logic_vector(1 downto 0) :=(others =>'0');
begin
count <=c;
process(clk, reset)
begin
if(rising_edge(clk)) then
if (c = "11") then
c <= "00";
end if;
c <= c+1;
end if;
if(reset = '1') then
c <= (others => '0');
end if;
end process;
end behvrl;

Now I need to use this 2-bit counter as components to implement a 4-bit counter
in STRUCTURAL VHDL....
Can you tell me how I should do it ?

If the said 2bit counter has only clk and reset inputs, the only way to make it work is that when count[1:0] isn't 11, disabling the clk to the upper 2bits.

Use a clock gating to get a clk to upper 2bit on and off depending on count[1:0] value as below.

clkgate block should be with a low-through latch(you need this latch to avoid the glitch on clk) and an AND gate like
This is a typical clock gating cell widely used.

hi,

thnks for your mail..
i am new to vhdl and so cannot understand your code..
can u plz upload a code in simple vhdl for the follwing problem..
write a STRUCTURAL vhdl code for 4 bit counter using 2 bit counters.
(The 2 bit counter must be written in behavioral vhdl.
The 4 bit counter must be written in structural vhdl..)
and if possible a block diagram of how to connect the 2 bit counters and extra
logic to form 4 bit counter..

thnks..

That isn't a code but it's a pseudo netlist and which part you don't understand ?
AND is an AND gate with a and b inputs and z output.
clk gate has inputs(clk, clk_en) and output (gclk) and contents of clk_gate is in the second code.
latch is a low-through latch where when clk_b is LOW, the latch becomes transparent from d to q, otherwise closed.
two_bit_cntr is what you have in your vhdl code.

Draw the logic and you'll understand it.

thnk u..i was alble to do it..