This code should synthesize fine.
The suggestion of RTL viewer was to give the user a bit more of an insight into how it will really look, and hopefully next time the qestion wont be so trivial.
I m sorry not synthesis error, it gives Syntax error near "nand"..
i think thats because it has to be stored in a signal before the second nand operation.
well as i see it nand is a primitive gate and can have only two input as defined but if you wish to have a 3 input nand gate to need to feed the output of earlier nand gate along with the third input to another nand gate......
Quartus has a primitive entity called nand3, so you are not allowed to create your own entity called nand3.
well as i see it nand is a primitive gate and can have only two input as defined but if you wish to have a 3 input nand gate to need to feed the output of earlier nand gate along with the third input to another nand gate......
This shows you do not understand FPGA architecture. In FPGAs, there are no gates at all, just 4/5/6 input Look up tables (depending on the chip). With more inputs, you can produce more "gates" per lut.