3input nand Gate using VHDL

[mangohaha]

Is this right? I want to make a 3 input nand gate....

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Code VHDL - [expand]
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library IEEE;
use IEEE.std_logic_1164.all;
 
entity nand3 is port(
x: in std_logic;
y: in std_logic;
z: in std_logic;
f: out std_logic);
end nand3;
 
architecture behav of nand3 is
 
begin
f <= (x nand y nand z);
 
 
end behav;

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Thanks....

 

[TrickyDicky]

Yes
How about compiling it yopurself to see the results in an RTL viewer?

 

[verylsi]

Hi,

Trickydicky is right ..
Because I dont think it will synthsize at first place.
and RTL view will give you a clear idea.

Good luck.

 

[TrickyDicky]

Hi,

Trickydicky is right ..
Because I dont think it will synthsize at first place.
and RTL view will give you a clear idea.

Good luck.

This code should synthesize fine.
The suggestion of RTL viewer was to give the user a bit more of an insight into how it will really look, and hopefully next time the qestion wont be so trivial.

 

[verylsi]

Hello Tricky,

I m sorry not synthesis error, it gives Syntax error near "nand"..
i think thats because it has to be stored in a signal before the second nand operation.

or am I missing something ??

 

[TrickyDicky]

ok yes - small syntax error
it should be:
f <= (x nand y) nand z;

- - - Updated - - -

Also - you cannot compile this in quartus because there is already a primitive called nand3 and it wont let you compile another one.

 

[verylsi]

I want to ask about the primitive in quartus..

Is it the entity name "nand3" which is matching with the primitive in quartus or any entity name with this logic will not be allowed by quartus ?

 

[mohi@608]

well as i see it nand is a primitive gate and can have only two input as defined but if you wish to have a 3 input nand gate to need to feed the output of earlier nand gate along with the third input to another nand gate......

 

[TrickyDicky]

I want to ask about the primitive in quartus..

Is it the entity name "nand3" which is matching with the primitive in quartus or any entity name with this logic will not be allowed by quartus ?

Quartus has a primitive entity called nand3, so you are not allowed to create your own entity called nand3.

well as i see it nand is a primitive gate and can have only two input as defined but if you wish to have a 3 input nand gate to need to feed the output of earlier nand gate along with the third input to another nand gate......

This shows you do not understand FPGA architecture. In FPGAs, there are no gates at all, just 4/5/6 input Look up tables (depending on the chip). With more inputs, you can produce more "gates" per lut.

 

[mangohaha]

thanks for all you guys' help....:grin: