32 ALU with 4 bit flags

[hbelkasmi]

hello,
I'm trying to implement a 32 bit ALU with Input a,b and output Result and 4 bit ALUFlags in system verilog.
the problem for me is that i Don't know how to implement the ALUFlags especially the Carryout.
should I use the one bit adder/sabstract .
Could any one help me
thank you in advance



this my code

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module Homework_4(
           input [31:0] a,b,  // ALU 32-bit Inputs                 
           input [1:0] ALUControl,// ALU Control
           output [31:0] Result, // ALU 32-bit Output
           output [4:0] ALUFlags //
    );
    reg [31:0] Result;
   
    always_comb
    begin
        case(ALUControl)
        2'b00: // Addition
           Result = a + b ; 
 
        2'b01: // Subtraction
    assign b = ~b+1
        Result = a + b ;
 
        2'b10: //  Logical and 
           Result = a & b;
 
        2'b11: // Logical or
            Result = a | b;
 
          default: Result == 0 ; 
        endcase
 
 
    end
 
endmodule

---

 

[ads-ee]

for a carryout you need an extra bit...

---

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logic [31:0] a, b;
logic [31:0] result;
logic carry;
 
always_comb begin
  {carry, result} = a + b;
end

---

two 32-bit numbers added together can have a 33-bit result depending on the inputs.

- - - Updated - - -

A nice way to perform subtraction is to not have an extra addr.

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Code Verilog - [expand]
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assign b = ~b+1 // extra add operation required
Result = a + b ;

---

instead remember 0b01+0b01 = 0b10, so taking advantage of adding two binary 1's gives you a 1 in the next bit to the left...

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logic [31:0] a, b;
logic [31:0] result;
logic carry;
logic throw_away_bit;
 
always_comb begin
  {carry, result, throw_away_bit} = {a,1'b1} + {~b,1'b1};
end

---

by appending a 1 to the end of the numbers being added you get the +1 for essentially just an extra carry chain delay (almost a freebie) instead of needing an entire 32-bit adder. Much more efficient with resources and timing delay this way.

I probably gave too much away for a homework problem.

 

[hbelkasmi]

Hello,

ok thanks for help
I will try and give you a feedback

thanks a lot

 

[hbelkasmi]

Hello,

there are conditions for overflow
// condition for overflow:
//-the ALU is performing addition or subtraction (ALUControl1 = 0)
//-A and Sum have opposite signs, as detected by the XOR gate and as detected by the XNOR gate
//-either A and B have the same sign and the adder is performing addition (ALUControl0 = 0) or A and B have opposite signs and the adder is performing subtraction (ALUControl0 = 1).

like shown in the atached file.
i tried to write it in system verilog like this:
if ((~ALUControl[1])&
(a^Result[31])&
(a[31]~^b[31]~^ALUControl[0]))
ALUFlags[0]=1;
else
ALUFlags[0]=0;

but i have doubt about (a^Result[31]) as A is 32 bit and Result[31] is one bit.

So could you tell me if i am on the right track.

thanks for your help

Regards

 

[ads-ee]

I have no clue what this is supposed to be.

if ((~ALUControl[1])&
(a^Result[31])&
(a[31]~^b[31]~^ALUControl[0]))

You are using bitwise operators for logical operations?

Maybe you should show us what the boolean operations you are trying to implement, so we can compare your code to it.

As you are using bitwise operators and using the result as a logical expression you have to understand things like
a ^ Result[31] is only false if the expression becomes 31'b0.

This is illegal syntax (a[31]~^b[31]~^ALUControl[0], and I'm not really sure what you are trying to accomplish without the actual boolean equations.

- - - Updated - - -

Edit..

Also use whitespace, it makes code more legible.

Iamsureyoufindreadingrunonsentencesdifficultduetothelackofwhitespace.

 

[hbelkasmi]

Hello,

I had those errors, i tried a lot to correct but i didn't get any thing


** Error: (vlog-13069) C:/Users/hbelk/Desktop/Homework_4/Homework_4.sv(26): near "=": syntax error, unexpected '=', expecting ++ or --.
** Error: (vlog-13069) C:/Users/hbelk/Desktop/Homework_4/Homework_4.sv(31): near "2": syntax error, unexpected INTEGER NUMBER.
** Error: (vlog-13069) C:/Users/hbelk/Desktop/Homework_4/Homework_4.sv(40): near "2": syntax error, unexpected INTEGER NUMBER.
** Error: (vlog-13069) C:/Users/hbelk/Desktop/Homework_4/Homework_4.sv(53): near "endmodule": syntax error, unexpected endmodule.

and here is my code in the attached image


thanks a lot


Regards,

 

[FvM]

Obviously elementary SV syntax errors. Please post complete module code instead of snippets in screen shot.

As a general hint, focus on the first error message, consider how it's brought up. Often the fault is not in the respective line but in the context, e.g. missing module or block statement, missing end or instruction delimiter somewhere above.

 

[hbelkasmi]

Hello FvM
here is my code

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// condition for overflow:
//-the ALU is performing addition or subtraction (ALUControl1 = 0)
//-A and Sum have opposite signs, as detected by the XOR gate 
//-either A and B have the same sign and the adder is performing addition (ALUControl0 = 0) or A and B have opposite signs and the adder is performing subtraction (ALUControl0 = 1).
 
module Homework_4(
           input [31:0] a,b,  // ALU 32-bit Inputs                 
           input [1:0] ALUControl,// ALU Control
           output [31:0] Result, // ALU 32-bit Output
           output [4:0] ALUFlags // N-Z-C-V
    );
   reg [31:0] Result;
   logic [31:0] B ;
   logic cout;
   assign B = ALUControl[0] ? ~b : b;
   
    always_comb
 
    begin
        case(ALUControl)
 
2'b00: {cout, Result} = a + B;        
    //Overflow
    ALUFlags[0] = ((a[31]^Result[31])&(a[31]~^B[31]~^ALUControl[0]))? 1 : 0;
    //Carry out 
     ALUFlags[1] =(cout&ALUControl[1])? 1:0;
        
2'b01: {cout, Result} = a + B;
    // Overflow
     ALUFlags[0] = (a[31]^Result[31])&(a[31]~^B[31]~^ALUControl[0])? 1 : 0;     
    //Carry out 
    ALUFlags[1] =(cout&ALUControl[1]) ? 1 : 0;
 
2'b10:  Result = a & b;
 
2'b11: Result = a | b;
 
    endcase
 
    //Zero
     ALUFlags[2] = (Result == 32'b0) ? 1:0;
        
    // Negartive
   
     ALUFlags[3] =(Result[31]) ? 1:0;
endmodule

---

I am Always not able to resolve the errors

thanks

 

[FvM]

Learn Verilog!

- case construct needs begin end if multiple statements are used per case item
- always_comb must not include latches or registers. You have (probably unwanted) latches in your case construct. Every variable must be assigned for all cases.
- missing end statement of always block