Please Help to Design a simple low power output stage.

[Grecs]

So I have a folded cascode PA working in A class and i have an output of 2V before the matching network. If I just drive it with an L matching network to a 50 ohm load I get at best 100mV output. I assume the culprit is the big output resistance of the folded cascode (measured 870-4700j). I want a simple low power output stage so that I can achieve at least 250mV on the 50 Ohm.

I tried a simple Source follower but I got trouble biasing it as I dont have DC on my output. Any help please? I am stuck a lot of days.

 

[jiripolivka]

What is your signal frequency? For your task I would use a simple transistor stage with a 4:1 output transformer to get a good match to 50 Ohms.
If your "PA stage" is working well with 2 V peak output (across what impedance?), it should be again easy to use a 4:1 transformer to get 0.25V across 50 Ohms.

 

[Grecs]

I work at 2.4Ghz.

My PA stage seems to work fine but I can control the peak and lower it if its a problem (Its just a trade off between Pin and Ampification). The 2V peak is what I got with a transient analysis before the Matching network I used and I am pretty sure its in saturation region. I dont understand your question (across what impedance?).

The paper I am working on doesnt mention anything about an output stage and simply drives the output of the common gate PMOS of the folded Cascode topology to an L matching Network and I did that and all I got was what I mentioned. I can clearly see some other tranzistors(2 or 4 cant really see clearly) in layout except the ones in the schematics on paper so I guessed that there is a buffer that doesnt get mentioned or something else.

So my problem basically is that with that approach I cant get a satisfactory 1dB compression point, or reach 1mW output. So I am searching for a way to get that swing to the 50ohms.

S parameters and impendance matching are checked with Spectre.

Thanks for answer.

 

[jiripolivka]

I work at 2.4Ghz.

My PA stage seems to work fine but I can control the peak and lower it if its a problem (Its just a trade off between Pin and Ampification). The 2V peak is what I got with a transient analysis before the Matching network I used and I am pretty sure its in saturation region. I dont understand your question (across what impedance?).

The paper I am working on doesnt mention anything about an output stage and simply drives the output of the common gate PMOS of the folded Cascode topology to an L matching Network and I did that and all I got was what I mentioned. I can clearly see some other tranzistors(2 or 4 cant really see clearly) in layout except the ones in the schematics on paper so I guessed that there is a buffer that doesnt get mentioned or something else.

So my problem basically is that with that approach I cant get a satisfactory 1dB compression point, or reach 1mW output. So I am searching for a way to get that swing to the 50ohms.

S parameters and impendance matching are checked with Spectre.

Thanks for answer.

I have a problem to advise: I do not use modeling. My experience is rather practical.
A good RF transistor with fT > 3 GHz should easily generate >+10 dBm to a 50-Ohm load. To match the output impedance I used a 4:1 impedance transformer; at 2.4 GHz my preference is to use coaxial resonators.

If your model is good but for the final stage, build the circuit and tune it. For +10 dBm output you will need ~30 mA DC current.