3 terminals resistor or a biased resistor

While designing layout of analog circuit, I came across a resistor with three terminals in the schematic. The third terminal was connected to the bulk or the substrate which was in turn biased (vdd or vss). Can anyone explain me why this resistor had three terminals, what is its advantage and what if we have used a simple two terminal resistor instead of this, could this lead to any difference?

is that potentiometer?
mostly potentiometer has 3 terminals, 1 is connected to vcc or vdd, 1 to ground, middle one is used for different voltage level.


if you design the circuit with series resistance, it might be have same voltage at source without any voltage drop on STARTING.

hetirajhimanshu said:

While designing layout of analog circuit, I came across a resistor with three terminals in the schematic. The third terminal was connected to the bulk or the substrate which was in turn biased (vdd or vss). Can anyone explain me why this resistor had three terminals, what is its advantage and what if we have used a simple two terminal resistor instead of this, could this lead to any difference?

Click to expand...

When a resistor (a design, or intended resistor - as opposed to a parasitic resistor) characteristics depend on voltage conditions of its environment, a third terminal can be used.
For example, a resistor formed by a well - its resistance and capacitance to the substrate are dependent on the voltage on the substrate (or the well enclosing the resistor):
- resistance is affected by the depletion width (and hence resistor effective thickness and resistance value) modulation by the voltage on a p-n junction
- capacitance is a capacitance of a p-n junction and hence voltage-dependent

In contrast, resistors formed by metals (or by high resistivity materials in the BEOL) have their resistance values independent on the voltages on the nets, and their capacitance is handled pretty accurately by parasitic extraction tools (parasitic extraction tools do not normally extract capacitances of the p-n junctions).
So, these resistors use 2-terminal SPICE models, usually.

Even without DC-active model elements the third
terminal lets resistor body capacitance be assigned
to an arbitrary node. This matters to parasitics-aware
RF simulations. If the resistor is junction-isolated then
there's even more to it, diode(s) need their connectivity
assigned and a voltco functionality can be modeled.

dick_freebird said:

Even without DC-active model elements the third
terminal lets resistor body capacitance be assigned
to an arbitrary node. This matters to parasitics-aware
RF simulations. If the resistor is junction-isolated then
there's even more to it, diode(s) need their connectivity
assigned and a voltco functionality can be modeled.

Click to expand...

dick_freebird -

if we assign a parasitic capacitance to an arbitrary node (as opposed to a node that is capacitively coupled through this parasitic capacitance) would lead to arbitrary post-layout simulation results - do you agree?

Max

Arbitrary in the sense that you get to represent
what you understand about the connectivity to the
"plate" beneath the resistor. As opposed to "gnd!" or
"sub!" and no ohms, no neighbor noise injection
and so on, choices made for you without recourse
(if at all) in more primitive schemes.

So no, do not agree.

dick_freebird said:

Arbitrary in the sense that you get to represent
what you understand about the connectivity to the
"plate" beneath the resistor. As opposed to "gnd!" or
"sub!" and no ohms, no neighbor noise injection
and so on, choices made for you without recourse
(if at all) in more primitive schemes.

So no, do not agree.

Click to expand...

dick_freebird -

I have a hard time figuring out what you said.

Under "arbitrary" I understand "selected randomly" - is this different from your definition of "arbitrary"?

I believe that parasitic capacitance should be assigned (connected) to a node/net that is really capacitively coupled to the resistor body.

Hey guys I am not still cleared @timof and @dick_freebird - can u guys please elaborate ?

Vraj said:

is that potentiometer?
mostly potentiometer has 3 terminals, 1 is connected to vcc or vdd, 1 to ground, middle one is used for different voltage level.


if you design the circuit with series resistance, it might be have same voltage at source without any voltage drop on STARTING.

Click to expand...

It is surely not a potentiometer, u cant fabricate a potentiometer in an integrated chip

hetirajhimanshu said:

Hey guys I am not still cleared @timof and @dick_freebird - can u guys please elaborate ?

Click to expand...

Please read my first post in this thread, it is pretty clear, I hope.

If not - can you ask specific questions, as I do not see what I should elaborate on?

timof said:

Please read my first post in this thread, it is pretty clear, I hope.

If not - can you ask specific questions, as I do not see what I should elaborate on?

Click to expand...

For my design it is recommended to use polysilicon resistor and not an n well resistor, so then why it has three terminals? I think that as we are designing an integrated monolithic design, so substrate is same and hence the third terminal is for the body or bulk of the resistor on which poly Si is to be fabricated. correct me if I am wrong?

Arbitrary != random. Random means you have no
authority over the assignment; arbitrary means you
have full authority (and responsibility).

Because you could place your poly resistor over psub,
nwell, and could express the bottom-plate-to-world
capacitance (and the R, L and series/shunt-C that
lie in the path), the third terminal (or, a property
field that assigns the node connection, perhaps with
a sensible default) is needed to enable you to express
that reality as best you are able.

hetirajhimanshu said:

... polysilicon resistor ..., so then why it has three terminals

... the third terminal is for the body or bulk of the resistor on which poly Si is to be fabricated. correct ...?

Click to expand...

You are quite right.
This poly resistor can lie over substrate or over n-well, in any case there will be a parasitic SOS (;-) instead of MOS) capacitance between the resistor and the bulk below it, which can be modeled if the 3^rd terminal is known. By this a good parasitic capacitance estimation can be achieved before parasitics extraction, which is welcome already for schematic simulation. During parasitics extraction after layout, the resistor's parasitic cap will be extracted and exchanged against the aforesaid modeled value.

For poly resistors the underlying bulk voltage doesn't really matter a lot, because AFAIK there's no semiconductor junction involved between them (if one prescinds from a voltage-dependent space-charge region between bulk and SiO₂ below the poly resistor).

hetirajhimanshu said:

For my design it is recommended to use polysilicon resistor and not an n well resistor, so then why it has three terminals? I think that as we are designing an integrated monolithic design, so substrate is same and hence the third terminal is for the body or bulk of the resistor on which poly Si is to be fabricated. correct me if I am wrong?

Click to expand...

No, there is no node created by parasitic extraction tool inside the body of the resistor.
The third terminal of a three-terminal resistor resistor is the underlying well, and a node (instance pin) would be placed in the well.
The voltage between first two terminals (PLUS/MINUS or POS/NEG) and the third terminal (well) will affect the parasitic capacitance between the poly resistor body (poly line) and the well.
Due to (relatively) low doping of the well applied voltage will affect the depletion/accumulation of free carriers in the well, near its interface with the oxide, and hence affect its capacitance.
Three-terminal resistor model means that this voltage-dependent capacitance is characterized for this technology, and parasitic extraction tool does not extract it (this is called "device blocking" in parasitic extraction).
Conductivity / resistivity of the polysilicon resistor will not be affected (in a first order approximation), but not because there is no p-n junction, but because poly is doped to a very high level so that poly depletion and accumulation effects are not significant (in poly resistor - but not in MOS gate poly case).