No, that's ok.Is there any harm in connecting the capacitor substrate to T2 for example?
Bulk must be connected to GND.I have a problem here in 3-terminal capacitors. If I connect the bulk to terminal 2 for example and this terminal is not connected to GND I will get multiple stamped connection problem.
Is it an NMOS? If so, its bulk also must be connected to GND (if it's not a double||twin||triple well process).Also I have a transistor that its bulk is connected to something but not GND. This also causes multiple stamped connection problem.
Bulk must be connected to GND.
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If I have three terminals capacitor and want to connect 2 terminals together (and not to GND).Is this possible?
I didnt get it. If I have three terminals capacitor and want to connect 2 terminals together (and not to GND). Is this possible? You said in another post that it is possible.
My opinion is negative to this...The third terminal of a process capacitor should be always connected to sub!
If your process doesn't include or support a model for the interface of p-substrate (sub!) and ground (VEE/GND) such as subc in various IBM's technologies then you should connect the third terminal to VEE.Now,suppose that you have somewhere in your schematic a cap from a node X to VEE.In this case you can short-circuit the two common terminals of the capacitor and connect them to VEE.I suppose erikl was implying this case when said yes above.
In my process, the schematic has 3 terminals. In layout two terminals and I have to create PD_C to connect the substrate.
Now I have another question, If I left the substrate node in the schematic floating and I still have the expected simulation results, is there any problem?
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