3 stage timer design (reworded - new diagram)

[cliffclivin]

Hello

I have some experience building electronic kits as a kid - radio's, transmitters, amp's etc. Later at University I was taught aspects of digital design using Electronics workbench - such as logic gates, flip flops, binary adders etc

I have a basic working knowledge but with some gaps. My main problem is I do not have electronics workbench or university lecturers handy to help...

I am trying to build a simple timer that cycles between 3 set delays, while energising two relays. One relay is on during the first time period, and the other relay is on during the last time period.

My idea is to use both sides of a D Type Flip Flop - and use the 2 flip flops to cycle between the three time periods. And use three 4017 Decade counters, and a 555 astable for clock pulses.

A capacitor & some diodes will 'set' both flip flops in the approprate mode on power-up so they are in sync. This is not shown on the diagram.

My idea:

Counter A starts count. Relay B is on

Counter A finishes count, resets flip flop A, Relay B is off. Starting Counter B.

Counter B finishes count, Resets flip flop B, Starting Counter C, Relay A turns on.

Counter C finished count, Sets Flip Flops A and B, Relay A turns off. Relay B Turns ON, Counter A starts count.

I have drawn a diagram of how I think this would be connected. I have only included connections for the logical side of things (Path of the clock pulses) I have only shown one output leg on all three 4017 counters for clarity.

**broken link removed**


Any help is much appreciated. Self education can be such a head ache!

Will this work as I expect it to? Any ideas welcome!

Cliff

 

[IanP]

Your diagram looks fine, but I have a question:
Why don't you use 3 x 555 (adjustable time from 1 to ..10s) and connect them in a sequence ie. one triggs the next one, the last one triggs the first one... ?
On power on you will need to trigg the first one and the whole sequence will run ..

 

[cliffclivin]

Thank you for your response - I'm glad it looks like it will work.

Could you please clarify what you mean by 'connecting three 555's in series'.

How would the circuit cycle between the delays? Would the Dual D Type Flip Flop still be used?Sorry if this is a very basic question.

This could be because I've oversimplified the diagram - it shows 3 set delays of 1 to 10 secs. The delays will be greater than this!

The diagram shows the three delays will be selected by three Decade Counters.. In reality, each decase counter will be made up of several decade counters (one for 1to 10 secs, on for 10 to 100 secs) The selected outputs from these will be connected via 'And' gates.

ie. Select 6 secs and 30 secs will produce a 36 sec wait for counter 1.

When the outout for 30 secs is high, along with the output for 6 secs, the Reset pulse will be sent to the flip flop via the 'And' gate.

I hope this is clear - can draw a diagram if not.

Thanks again for taking the time to help!

Cliff

 

[IanP]

It looks like 3 x 555 will do the job.
Here is an example on how a 555 generates a monostabile impulse:
**broken link removed**
Output from pin 3 can be connected to the input (pin2) of the next stage, and so on. What you will need is a RC network (reset-on-power-on) connected to pin 4 of the first 555 to start-up the sequence when the power is turned on ..

 

[cliffclivin]

I have had an idea suggested to me, which is very similar to your proposed soloution.

Your soloution involves linking 3 x 555 monostables in series so the three time periods are made from the 555's.

I would like for the three time periods to be independantly adjustable, and accuarte. By accurate I mean able to select the derised time delay through the use of 4017 counters.

So the new soloution involves linking the enable inputs of the counters in series, so each counter holds itself and starts the next counter.

One way is to utilize the enable input of the 4017. If the desired output is connected to the enable input, the counter will freeze when the output goes high. It can released only by reset (in what situation is starts counting from zero).

So first counter's output is connected to it's enable input and second counter's reset via an inverter. Then the first one's output is low until the counting reaches the selected output (it goes high the). Enable makes the counter freeze and releases next counter to count (not in reset situation any more). While the next counter is counting the third is held reset until the second counter reaches the seleced output value.

Then 2nd counter freezes and third is released for counting. When the third reaches the selected count, it will reset the first counter (no inverter here). The outputs for the relays are formed by combinational logic from the counter outputs. '

This sounds like a very elegant soloution. What d'ya think?
Many thanks,

Cliff

Added after 3 hours 43 minutes:

I have drawn a clear diagram showing the above suggestion.

**broken link removed**

It looks ok, but I have a question regarding counter three triggering counter one.

When the 10+ pulse comes from Counter Three, ithe pulse goes to Enable of Counter Three, So a steady signal holds Counter Three steady at 10+.

This steady signal is sent to the Reset of Counter One.

Doesnt Counter One need a short pulse to the Reset pin? Will the constant on signal from Counter Three hold Counter One in Reset Mode ?(Holding at Zero?)

So the upshot is the circuit would cycle through the three delays, then be held on permanent hold at counter one?

Or will the circuit cycle through the three delays continually?