You would use the 3-terminal model for anything RF
(presuming there's not an even more sophisticated
one offered) to represent the shunt-C distributed
across the resistor area, and "to where?".
There is no ohmic connection but there are still AC
currents.
The thin film resistor is also potentially a field MOS
gate and carries with it, in bad cases, a C-V swing
that adds nonlinearity to RF circuits. So a hard heavy
implant below, eliminates nonlinear AC currents (but
on the minus side, lowers the series resistance to
the field below the resistor - which can make the
effects of the shunt-C worse than (say) putting the
resistor over a lighter doped (high resistivity or even
intrinsic) region, which is a common thing for RF in
CMOS, both JI and SOI.
Device recognition rules and ERC are going to check
for consistency of construction between all of the
implants and so on. If you read the rules deck you
can probably figure out what it's complaining about
(although PCells placed from schematic ought to
deliver the sought consistency, "you break it, you
bought it" once you start touching polygons one
by one.