`timescale 1ns / 1ps
module samlagning_fradrattur(A0, A1, A2, A3, B0, B1, B2, B3, S0, S1, S2, S3, M);
input A0, A1, A2, A3;
input B0, B1, B2, B3;
reg BB0, BB1, BB2, BB3, C0;
input M;
output wire S0, S1, S2, S3;
wire C1, C2, C3, overflow;
initial
begin
assign C0 = 0;
assign BB0 = B0;
assign BB1 = B1;
assign BB2 = B2;
assign BB3 = B3;
if(M==1)
begin
assign BB0 =~BB0;
assign BB1 =~BB1;
assign BB2 =~BB2;
assign BB3 =~BB3;
if(BB0==0)
assign BB0 =~BB0;
else if(BB1==0)
begin
assign BB0 =~BB0;
assign BB1=~BB1;
end
else if(BB2==0)
begin
assign BB0 =~BB0;
assign BB1 =~BB1;
assign BB2 =~BB2;
end
else if(BB3==0)
begin
assign BB0 =~BB0;
assign BB1 =~BB1;
assign BB2 =~BB2;
assign BB3 =~BB3;
end
end
end
full_adder F0(A0, BB0, C0, S0, C1);
full_adder F1(A1, BB1, C1, S1, C2);
full_adder F2(A2, BB2, C2, S2, C3);
full_adder F3(A3, BB3, C3, S3, overflow);
endmodule