2nd order sigma delta converter Comparator Block

[Irfansw07]

comparator block

Hello

I am designing Comparator which has to be used in 2nd order sigma delta converter.When my schematic Comparator is compare with Verilog A comparator than the output waveform of both is not same as the schematic Comparator output is more dense tha Verilog A Comparator....

Can anyone please help me in giving answer why it is happening and what has to be done in Schematic Comparator so that there is same density output waveform as Verliog A block one ?

Thanks in advance

 

[JoannesPaulus]

is one clocked while the other is not?

 

[Irfansw07]

For both the block there is same clock.....
I am giving same signal,same reference voltage and same clock for both the block