Hi
thanks for your reply
I have to implement 2D fft in VHDL . I have 1D fft vhdl code, now how do I convert it to 2D fft??
Hi
Can I apply below input that has been applied to 1D fft, to the 2D fft??
the input is like array of vector form i.e.
0000000000010000
1000111000101001
0100101101000001
0011010011100101
0101001100101101
0001110000110001
1101010000001011
0011111100110010
0100111010001111
0010000001011010
0010111010100111
0010110000000010
1001001110000010
0001110000100100
1011101110000101
0010010101001100
1101010010111111
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
Hi
thanks
I had 16 input for my 1d fft ,Now for 2D fft I had assumed that 16 input into 4*4 matrix.but they are defined in the same way as it was for fft 1D.
Now I am calculating the 1D fft then transposing the 1D fft output then again calculating the 1D fft on those and at last again transposing them.
suppose below is my output of 16 point 1D fft.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
I am assuming above as
1 5 9 13
2 6 10 14
3 7 11 15
4 8 12 16
Now for transposing I am doing like this
1
5
9
13
2
6
10
14
3
7
11
15
4
8
12
16
and this transposed output I am applying as the input to the again to the fft
and at last again transposing.
Is this correct???
please help
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Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.Numeric_Std.all; entity sync_ram is port ( clock : in std_logic; we : in std_logic; address : in std_logic_vector(7 downto 0); datain : in std_logic_vector(15 downto 0); dataout : out std_logic_vector(15 downto 0) ); end entity sync_ram; architecture RTL of sync_ram is type ram_type is array(0 to 15,0 to 15) of std_logic_vector(15 downto 0); signal ram : ram_type; signal read_address : std_logic_vector(7 downto 0); begin RamProc: process(clock) is begin if rising_edge(clock) then if we = '1' then ram(to_integer(unsigned(address))) <= datain; end if; read_address <= address; end if; end process RamProc; dataout <= ram(to_integer(unsigned(read_address))); end architecture RTL;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 signal row_i : integer range ram_type'range(1); signal col_i : integer range ram_type'range(2); ..... RamProc: process(clock) is variable row, col : integer; begin if rising_edge(clock) then row := to_integer( unsigned( address(7 downto 4) )); col := to_integer( unsigned( address(3 downto 0) )); if we = '1' then ram(row, col) <= datain; end if; row_i <= row; col_i <= col; end if; end process RamProc; dataout <= ram(row_i, col_i);
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