transferring from clock domain

[sun_ray]

I have two clocks name Clk1 and Clk2 from the same clock source and the frequencies of both the clocks being same. But there is an unknown phase difference between the Clk1 and Clk2. How can I safely transfer the data from domain of Clk1 to Clk2?

 

[rca]

The phase is change inside a macro block, with unknown timing ?

 

[sun_ray]

The Clk1 and Clk2 has same frequency and Clk1 and Clk2 has only phase difference between them. This phase difference is not known and the phase difference can change also from time to time.

 

[AdvaRes]

Hi,
you can use a 2 or 3 Flip flop synchronizer for clock domain crossing.

 

[sun_ray]

Hi,
you can use a 2 or 3 Flip flop synchronizer for clock domain crossing.

We want to safely pass data. How a 2-3 flop synchronizer will work in this case?

 

[Prashanthanilm]

You can use Buffer !!

 

[sun_ray]

You can use Buffer !!

In which path shall you use buffer and how will buffer solve the problem?

 

[Prashanthanilm]

I have two clocks name Clk1 and Clk2 from the same clock source and the frequencies of both the clocks being same. But there is an unknown phase difference between the Clk1 and Clk2. How can I safely transfer the data from domain of Clk1 to Clk2?

First of all, What is CLK1 and CLK 2? -> Clocks in different paths but the source is same!!S

 

[rca]

Well in this case, you manage that as asynchronous clocks, and then the two flip flops to clock domain transfers is required as usual.

 

[sun_ray]

First of all, What is CLK1 and CLK 2? -> Clocks in different paths but the source is same!!S

Yes the source is same but the clocks are sent to different designs. Though the source of Clk1 and Clk2 are same they have an unknown phase difference between them. Is the problem clear?

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Well in this case, you manage that as asynchronous clocks, and then the two flip flops to clock domain transfers is required as usual.

This may not be the right solution.

 

[Prashanthanilm]

The delays may be the due to the path from the source right?.

Whether the path taken by CLK 1 and CLK 2 are same with respect to Source and also whether there is any presence of any combinational circuit in the path.

 

[rca]

Sun_ray could you clarify, by the clock is send to different designs?
Do you mean the clk 1&2 have a different phase because you defined two clocks on your synthesis?
You could not create a single create clock during the synthesis for some specific design constraint?

 

[sun_ray]

The delays may be the due to the path from the source right?.

Whether the path taken by CLK 1 and CLK 2 are same with respect to Source and also whether there is any presence of any combinational circuit in the path.

I do not know that much of details whether there is any presence of combinational circuit or not. I also do not know whether path taken by CLK 1 and CLK 2 are same with respect to Source or not.

But I infer that the phase difference is due to different paths taken by Clk1 and Clk2 and there may be cobinationa circuot present in the paths of Clk1 and Clk1 causing the phase difference.

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Sun_ray could you clarify, by the clock is send to different designs?
Do you mean the clk 1&2 have a different phase because you defined two clocks on your synthesis?
You could not create a single create clock during the synthesis for some specific design constraint?

Yes, the clock is send to different designs. No, I do not mean the clk 1&2 have a different phase because you defined two clocks on your synthesis. It is not that I could not create a single create clock during the synthesis for some specific design constraint.

 

[lubee]

in order to be safe, you can extend one cycle of the signal at the clk1 domain into two cycles and use 2 FFs to synchronize it to the clk2.

 

[sun_ray]

in order to be safe, you can extend one cycle of the signal at the clk1 domain into two cycles and use 2 FFs to synchronize it to the clk2.

Can you please draw a diagram to represent your solution?

 

[sun_ray]

Prashanthanilm

I am waiting for your reply still.

Regards

 

[pramodm]

I did not clerly understand following statements


"two clocks name Clk1 and Clk2 from the same clock source and the frequencies of both the clocks being same"
"the clock is send to different designs"

i think, No need of a synchronization circuit between the paths of two designs.

If same 'Clk' is used by two designs(blocks), as Clk1 for one design(block1) and as Clk2 for other design(block2). then No need of a synchronization circuit between the paths of two designs(block1 & block2). Clk1 & Clk2 are same frequency as 'Clk'. the phase diff between Clk1 & Clk2 are diff in clock distribution delay(Clock Skew). generally tools will take care of 'Clock Skew'. you can also control by controlling blocks placement.

If Clk1 & Clk2 are same frequency and generated from same source 'Clk' of diff frequency, use proper clock generater circuit(pll).

thanx

 

[sun_ray]

I did not clerly understand following statements


"two clocks name Clk1 and Clk2 from the same clock source and the frequencies of both the clocks being same"
"the clock is send to different designs"

i think, No need of a synchronization circuit between the paths of two designs.

If same 'Clk' is used by two designs(blocks), as Clk1 for one design(block1) and as Clk2 for other design(block2). then No need of a synchronization circuit between the paths of two designs(block1 & block2). Clk1 & Clk2 are same frequency as 'Clk'. the phase diff between Clk1 & Clk2 are diff in clock distribution delay(Clock Skew). generally tools will take care of 'Clock Skew'. you can also control by controlling blocks placement.

If Clk1 & Clk2 are same frequency and generated from same source 'Clk' of diff frequency, use proper clock generater circuit(pll).

thanx

Please see the first post in this thread. There the question was stated. Here the difference in phases between the clocks is not fixed or defined and hence can vary from time to time. Do you think that no solution is required in this case? Please see my next thread titled safely passing data.

 

[Prashanthanilm]

"I do not know that much of details whether there is any presence of combinational circuit or not. I also do not know whether path taken by CLK 1 and CLK 2 are same with respect to Source or not.

But I infer that the phase difference is due to different paths taken by Clk1 and Clk2 and there may be cobinationa circuot present in the paths of Clk1 and Clk1 causing the phase difference."

Sunray,

Sorry for the late reply.

If you don't know the details how you can check it?
If there is no ckt between them , then the delay will be very less can be approximated to ignore.

I don't understand what is the exact requirement? Since the information is less what do you want to infer from this?

 

[sun_ray]

"I do not know that much of details whether there is any presence of combinational circuit or not. I also do not know whether path taken by CLK 1 and CLK 2 are same with respect to Source or not.

But I infer that the phase difference is due to different paths taken by Clk1 and Clk2 and there may be cobinationa circuot present in the paths of Clk1 and Clk1 causing the phase difference."

Sunray,

Sorry for the late reply.

If you don't know the details how you can check it?
If there is no ckt between them , then the delay will be very less can be approximated to ignore.

I don't understand what is the exact requirement? Since the information is less what do you want to infer from this?

I was once asked this question. So it is not that I am finding such an issue now. Please take it as a theoretical question and answer this.

Regards