How to lower Vth of MOSes

[shaikss]

Hi,

I want to lower Vth of MOS in my design.
I am using 4-T cell rectifier using gate cross coupled architecture. I have attached the snapshot of the same.
This rectifier is for low power applications. So my input is in the range of 200mV.
For this reason, I want to lower the Vth of MOS device.

I tried to lower the Vth by biasing the gate voltage - That is, I have connected a external dc voltage source to the gates of MOSes.
With this, I am able to see some reasonable output. But I don't want to use external supply.
Somehow, I want to generate the biasing voltage within the rectifier without using external supply.

How is this possible? Please give me some hints to implement.

I have come across, some structure, second attachment. But couldn't get expected results. What may be the issue in the design?



Thanks in advance.

 

[varunkant2k]

Hi Shaikss, MOSFET Vth, can be increased by backgate. But I did not heard about decreasing the Vth instead foundry provide you some low Vth devices.
I understand that you already aware that, low Vth causes more power loss. What is power supply you are using, anyway?
There are various ways to use 200mV input.

 

[shaikss]

Hi Shaikss, MOSFET Vth, can be increased by backgate. But I did not heard about decreasing the Vth instead foundry provide you some low Vth devices.
I understand that you already aware that, low Vth causes more power loss. What is power supply you are using, anyway?
There are various ways to use 200mV input.

Hi Varun,

RF input power is extracted from an antenna which is in few microwatts to milli watts.
So, on average, voltage input to rectifier is around 300mV which is less than 400mV.
It is required to lower Vth in order to rectify my input RF voltage.

 

[varunkant2k]

Or If you can use LNA , I think that will be more efficient. have you thought that.

 

[Braski]

i think it's not possible to efficiently lower vth.

 

[erikl]

You could perhaps use native MOSFETs if your process provides them.

 

[analog-designer]

Vth is a technology parameter which is defined bydoping concentration, implantation dosis of poly silicon and thickness of gate oxid. By applying an postive voltage at the gate, the surface of the semiconductor is inverted. Until the gate voltage is lower than vth the semiconductor is in weak inversion if voltage is higher than vth it is in inversion and a conductive channel propagates under the gate. In case of inversion the surface bending is larger than twice the volume potential whereby stationary acceptors remain and mobile carriers are displaced into the volume.
An increase of vth is affected by backgate biasing because the depletion layer between source and substrate is increased and additional stationary acceptors must be included in the depletion approximation.

Resulting: There is no chance to decrease vth by applying special opration points. Supporting erikl: Choose another device in your process are apply some sophisticated circuitry lika LNA.