Required: detail explanation on the WLM parameters

[ivlsi]

Here is below some part of the WLM file. Could anybody explain please each line of this file? Thank you
---------------------------------------------------

library(myWLM) {

/* zero wire-load */
wire_load("zero") {
resistance : 0;
capacitance : 0;
area : 1;
slope : 1;
fanout_length(1,2000);
}
}

library(2K_6LM) {
wire_load("2K_6LM") {
resistance : 1.2;
capacitance : 0.2;
area : 1;
slope : 1;
fanout_length(1,2000);
fanout_length(2,2500);
fanout_length(3,3000);
fanout_length(4,4000);
fanout_length(5,5000);
fanout_length(6,6000);
fanout_length(7,7000);
fanout_length(6,8000);
}
}

--------------------------------------------------

What files do include WLM?

 

[englishdogg]

I can share part of knowledge that i am aware of on WLM's.
Basically we need to model some value of R and C in the design to calculate net delay. Now in case of WLM based synthesis this comes from the library.
WLM's are basically look-up tables of fanout vs load and are applied on the design depending on the area consumed for that speific hierarchy.

IN WLM based synthesis depending on thw WLM available in the libraries you can also set a speific model to be used across the entire design. there are also different ways to calculate the net delay in different synthesis tools if the net is traversing multiple hierarchies and would have R and C values depending on area and mode of calulation.

Although nowadays not many use this and have moved to more of physical based caculation where R and C values are taken from the LEF and Captable files which are provided from foundry depending on the technology node. and these same files are also used for the same purpose in the flow further down which makes the accuracy beeter than WLM.

Most of the synthesis tools support it - RC-PLE, RCP, DC-T

Hope i could help

 

[ivlsi]

You wrote: "WLM's are basically look-up tables of fanout vs load" - ok, please take a look on the example of WLM I've provided in my first post on the thread... How can I understand this "Look Up Table"? What fanout corresponds to each load? Didd you mean that the load on the cell output pins is calculated in the terms of fanout? What does the 'fanout_length(1,2000)' mean?

What is a LEF file? What does it include? In which format? Could you provide an example of the LEF file?

What is a Cap-table file? What does it include? In which format? Could you provide an example of the Cap-table file?

 

[oratie]

fanout_length(2,2500) means, that for output pin with fanout equal 2, the wire length will be 2500. Then you need to multiply this wire length with capacitance : 0.2; or resistance. In such way you will able to calculate RC values for all wires.

This approach is based on statistical info (average wire length among different designs) and doesn't requires cell placement info (so it is easy, faster method, but not very accurate). The more precisely way is to use rough placement of the cells, then you will be able to precisely estimate length of each wire, and use Cap-tables for calculating real RC values. Cap-table just keeps RC data for each metal layers - no any relations to fanout or (just RC per wire width, wire spacing, metal layer number ...).

 

[ivlsi]

Thank you! BTW, why STA tools need WLM for post-layout checks?

Some companies create Custom WLM. What does it mean? How do they do that?

Do Synthesis tools choose WLM automatically according to the Gate Count of the design? As for the designer, should he/she only define a WLM Mode?

---------- Post added at 01:34 ---------- Previous post was at 01:21 ----------

Cap-table just keeps RC data for each metal layers - no any relations to fanout or (just RC per wire width, wire spacing, metal layer number ...)

How the tool knows which RC pair to take just from the cells placement? Does it calculate the wire length?

Could you please provide some short example of the Cap-Table - how does it looks like?

How much a placement of the cells could be changed after CTS and Routing?

 

[oratie]

why STA tools need WLM for post-layout checks? - no idea, i never used WLM for post-layout (post-route) checks.

Some companies create Custom WLM. - just to have more accurate WLM for their own designs. They did place (and route) of their design, collect info of all wires (fanout and length for each net) and generate average lengthg per fanout. For example, Synopsys Jupiter has such capability.

Do Synthesis tools choose WLM automatically according to the Gate Count of the design? The sinthesis tool has such capability. The question here - does provided WLM has different tables per gate count (or just one table for any design).

As for the designer, should he/she only define a WLM Mode? - Usually, yes. Still, it depends on WLM that you have (as stated above, it may be one simply table).

How the tool knows which RC pair to take just from the cells placement? Does it calculate the wire length? Yes, the tool that does placement (for example Synopsys DC-topographical or IC Compiler) is able to esimate each wire length after placement and before real routing. In this case, it needs Cap-table (Cadence) and TLUPlus (Synopsys), where it can find RC values per length/spacing/width.

Could you please provide some short example of the Cap-Table - how does it looks like? Sorry, I haven't example with me. You can find it in Cadence/Synopsys documentation. No any magic in these files, just RC values per predefined wire width, wire space etc.

How much a placement of the cells could be changed after CTS and Routing? - Usually, not much. Because, when we start placement, we reserve some free space for new cells (clock cells, additional buffers for hold fixing ...).

 

[ivlsi]

WLM has different tables per gate count (or just one table for any design).

So, what usually does happen? How many WLM models are usually supplied with STD Cell libraries? Are there WLM, which depend on geometry of the design? on gates-count?

Thank you!

 

[ivlsi]

WLM has different tables per gate count (or just one table for any design).

So, what usually does happen? How many WLM models are usually supplied with STD Cell libraries? Are there WLM, which depend on geometry of the design? on gates-count?

tool that does placement (for example Synopsys DC-topographical or IC Compiler) is able to esimate each wire length after placement

And what about the placement-not-aware tools like a regular Design Compiler from Synopsys? How do these tools know how to take the right values from the WLM? They are not aware of the wires length, are not them?

we reserve some free space for new cells (clock cells, additional buffers for hold fixing ...)

Could you give me some number (in %) how much space do you reserve for these purposes?

Thank you!

 

[englishdogg]

1. it's difficult to say how many WLMS are usually supplied with STD libraries- atleast i am not aware of any thumb rule; they are a part of the libraries not any separate
files. Yes, gates-count per say area for that specific module and not geometry of the design.

2. See if we talk about non-physical aware synthesis tools then they rely on WLM. But Cadence has a tool (RC-PLE) in which regular synthesis i.e. non-physical/placement based synthesis it uses LEF and Cap-table files to substitute WLM based synthesis. It is exactly the same synthesis flow but using lef/captables over WLM from library

 

[ivlsi]

Yes, gates-count per say area for that specific module and not geometry of the design.

From taking a look on the WLM, which I have, I don't see ever a clue about the gates count - there are only relations between a fanout and wire length. So, it's still not understood for me how WLM depends on gate-count... In the theory it's clear, but in the practice... Where is gate-count information stored in the WLM? Could you please provide an example or lines from your WLMs?

it uses LEF and Cap-table files

What's the LEF files? What info do they store?

Thank you!

 

[jeet_asic]

This will help you about LEF :

https://www.csee.umbc.edu/~cpatel2/links/641/slides/lect04_LEF.pdf

 

[oratie]

wire_load_selection(WireArea){
wire_load_from_area(0, 17134, "WLM8K");
wire_load_from_area(17134, 38552, "WLM16K");
}
wire_load("WLM8K") {
resistance : 0.00001 ;
capacitance : 1 ;
area : 0
slope : 0.0010
fanout_length(1,0.0011)
fanout_length(2,0.0019)
fanout_length(3,0.0029)
fanout_length(4,0.0040)
fanout_length(5,0.0053)
}
wire_load("WLM16K") {
resistance : 0.00001 ;
capacitance : 1 ;
area : 0
slope : 0.0011
fanout_length(1,0.0011)
fanout_length(2,0.0020)
fanout_length(3,0.0031)

As you can see, it contains two WLM tables for different size of design. Then, you can use DC command set_wire_load_selection WireArea.
Don't be confused, with wire_load_from_area. This area is not a physical area of your design (floorplan dimension). The WLM is used during pre-layout stage, so no any floorplan exist. This area is just a cell area (sum of all cell area, that present in your design), which corresponds to gate count (for example, one gate is a simply 2-input nand, so divide cell area by nand area = number of gates.)

 

[ivlsi]

Thank you! This explains a lot!

 

[englishdogg]

@ dmitryl

I agree with oratie on the area query that he answered. On LEF - the pdf pointed out by jeet_asic is equally helpful.

LEF files will be - technology lef, standard cell lef and macro lef's. Basically consists of physical information (layers, resistance, capacitance etc) about the technology. Standard cell lef / macro lefs will have the physical footprint of the cell.

Cap table files - include pure capacitance info - has two tables - basic and extended. Basic table info is usually used during the physical synthesis stage and extended further down the flow during extraction.

 

[birdy123]

Hi,

So many questions in a single place. Anyways.. Its difficult to explanin every thing here.FOr LEF in one sentance - its like *.lef - Library Exchange Format. Standard cells are often saved in this format. Cadence tools also often use this format. Synopsys tools normally use Milkyway format for standard cells.

FOr WLM -- its a big topic- I will check if I can find any proper material on this, I will forward that to you.

 

[birdy123]

Hi,

Please find the details in the following post. It should ANS all of your questions. If you still have any doubt- please feel free.

https://vlsi-expert.blogspot.in/2012/03/delay-wire-load-model-static-timing.html

 

[ivlsi]

Thank you!

 

[ivlsi]

I've read the articles, but still have a questions regarding to Structural WLM...
Here is a citation from the article: "Structural WLM is based on the information about neighboring nets rather than just fanout and module size information." So, what does it mean? Can anyone explain it in more details?
Thank you!