Design of OTA for DAC

[Ravinder487]

Hi all,
I want to design an OTA ,for my DAC, with these specifications:Laod Capacitance
50fF and settling time <1nS and slewrate >1V/nS.
Achieving these there specs seems to be extremely difficult to me .Please post your suggestions as soon as possible.It's urgent.

Thanks&regards,
Ravinder

 

[Braski]

uhm...
i think that you can first fix your slew rate..
you should have a slew rate of 1V/ns or greater, equal to 1 GV/ s. So, the current which the voltage-to-current converter has to source when a large signal applied is simply I=C*dV/dT = 50e-15*1e9 = 50e-6 = 50 uA. This is the maximum output current you have to set for your OTA. This current can be higher if you need a greater slew rate. 50 uA is the "minimum maximum" current.
Then you have to measure your settling time by applying a small signal, to avoid reaching the slew rate, and evaluate the settling time itself, ringing and correct it if necessary. However, i think that the settilng time spec is for a given voltage, isn't it? This is because if you apply a signal which makes the OTA to reach the slewing, the settling time is superimposed by the slew rate itself, because the OTA works at its max speed.

 

[Ravinder487]

uhm...
i think that you can first fix your slew rate..
you should have a slew rate of 1V/ns or greater, equal to 1 GV/ s. So, the current which the voltage-to-current converter has to source when a large signal applied is simply I=C*dV/dT = 50e-15*1e9 = 50e-6 = 50 uA. This is the maximum output current you have to set for your OTA. This current can be higher if you need a greater slew rate. 50 uA is the "minimum maximum" current.

But for 2-stage opamp slerate is determined by ratio of compensation capacitor and tail current of first stage rather than what u said,correct me if I'm wrong.

However, i think that the settilng time spec is for a given voltage, isn't it?

Yeah you are right,If OTA is slewing then settling time is soley dependent on slewrate(and hence on voltage step).Else it is dependent on phasemargin(may be on Bandwidth).

---------- Post added at 18:20 ---------- Previous post was at 17:06 ----------

Hi all this is problem I'm facing In designing OTA.I got slewrate of 10V/uS using bias current(Id) of 45uA.So I've increased the Id by 8 times then I need to increase W/L of second stage so that gm/Cgs of second stage is 10 times the gain bandwidth.If I increase W/L so will its Cgd increases(and gets added to Cc).So my slewrate(Id/Cc) isn't increasing by 8 times.
So it seems,to me,next to impossible to reach a slew rate of 1GV/S!!!!Please help me.

 

[lamoun]

Hi all this is problem I'm facing In designing OTA.I got slewrate of 10V/uS using bias current(Id) of 45uA.So I've increased the Id by 8 times then I need to increase W/L of second stage so that gm/Cgs of second stage is 10 times the gain bandwidth.If I increase W/L so will its Cgd increases(and gets added to Cc).So my slewrate(Id/Cc) isn't increasing by 8 times.
So it seems,to me,next to impossible to reach a slew rate of 1GV/S!!!!Please help me.

Why do you set the gm/Cgs of the second stage to 10 GBW, to make the OTA stable?

If this is necessary then you might have to use other architecture for the OTA so you can use a smaller Miller cap.

This is probably a very nice technique (haven't used it yet)
CMOSedu bad design 3

See page 21 on this too https://cmosedu.com/jbaker/papers/talks/Multistage_Opamp_Presentation.pdf

 

[Ravinder487]

yeah inorder to make OTA stable zero due to Cgs3 is placed beyond ten times GBW(as the pole has its effect from 0.1*its corner frequency) !!