2-stage differential amplifier output resistance - Cadence

[kerekuto]

I am trying to obtain the gain of a 2-stage op-amp, but it seems that the output resistance is far less than what i'm expecting. The output resistance is supposed to be the parallel combination of the output resistance of the pmos and nmos, right? in Results Browser, the gds value of the pmos is 2.21E-5 and for the NMOS is 1.94E-5. Therefore, I should be expecting an output resistance of around 24Kohms. In order to verify this, I am instantiating the op-amp in a testbench with the input terminals grounded, and an ac current source with magnitude of 1 A connected at the output. Measuring the voltage in an AC analysis should plot the output resistance of the opamp, but the magnitude is only 16.6Kohms. Is gds the right parameter to calculate the output resistance? Why am I getting such a big difference from what I'm expecting?

Thanks in advance!

 

[Braski]

30% from hand calculation is not that much however. In this case i don't know what exactly tell you, is your amp biased properly?

 

[kerekuto]

all transistors are in saturation. it frustrates me that it should be just a parallel combination of resistances, i don't know where is the difference coming from.

 

[erikl]

Is gds the right parameter to calculate the output resistance? Why am I getting such a big difference from what I'm expecting?

Because you didn't consider r_o = δV_DS/δI_D, an additional parallel output resistance due to the channel length modulation factor λ, which causes the I_D vs. V_DS (saturation) characteristic not to be parallel to the x-axis but showing a (small) positive gradient.

In 1^st approximation, ro ≈ 1/λI_D = V_E/I_D , where V_E is the so-called "Early Voltage".

Hence the output resistance for each transistor is (1/g_ds || r_o) , s. e.g. Behzad Razavi "Design of Analog CMOS Integrated Circuits" 2.4.3 MOS Small-Signal Model .

 

[LvW]

Because you didn't consider r_o = δV_DS/δI_D, an additional parallel output resistance due to the channel length modulation factor λ, which causes the I_D vs. V_DS (saturation) characteristic not to be parallel to the x-axis but showing a (small) positive gradient.

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Hi Erik, for my opinion, the element 1/gds (as mentioned by kerekuto) does already model the channel length modulation since it reflects the finite slope of the ID-VDS characteristics.

 

[erikl]

Hi LvW, right, it seems that this is handled differentially in various CMOS books, depending on the MOS small signal model used. Razavi, I think, differentiates between g_ds and r_o throughout his book, whereas Allen/Holberg and Binkley include the CLM effect into their g_ds definition.

I just wanted to point out the possibility, that the OP's g_ds value wouldn't include the CLM effect.

 

[steadymind]

In order to verify this, I am instantiating the op-amp in a testbench with the input terminals grounded, and an ac current source with magnitude of 1 A connected at the output. Measuring the voltage in an AC analysis should plot the output resistance of the opamp

by grounding the inputs do you still have the right bias voltage on your output stage. the grounding should be an AC ground (ie) some common mode voltage on the inputs to maintain bias. compare the DC voltage at output between the differential operation and output resistance measurement. gds varies with vds across the devices.

 

[kerekuto]

by grounding the inputs do you still have the right bias voltage on your output stage. the grounding should be an AC ground (ie) some common mode voltage on the inputs to maintain bias. compare the DC voltage at output between the differential operation and output resistance measurement. gds varies with vds across the devices.

Good point. However, i just double checked the vds values of both measurements and they are the same. The input differential pair is properly biased in both test benches.

I found a post in another forum with a problem similar to mine, but no clue on what was the outcome:


Any other suggestions?

 

[LvW]

Kerekuto,

is there any internal feedback loop connected to the output? In this case the output impedance may drastically change in comparison to simply calculating 1/gds.

 

[kerekuto]

LvW, do you mean compensation? I am using cascode compensation, and since it consist of a capacitor it doesn't change the output impedance at low frequencies. At this point I am trying anything that comes to mind and even disconnected the compensation from the output. That didn't make a difference.

If you meant about a diode connected transistor in one of the output transistors, the answer is no. As Braski mentioned earlier, the difference between from what I am expecting (24Kohms) and what I'm measuring (16.6Kohms) is roughly 30%, but still too large to just ignore.

 

[LvW]

..............
the difference between from what I am expecting (24Kohms) and what I'm measuring (16.6Kohms) is roughly 30%, but still too large to just ignore.

OK, on the other hand, don't forget that in ac analysis all capacitive effects and pathes are taken into account - contrary to 1/gdc calculation. Perhaps this can explain the difference?

 

[FvM]

If you reduce the transistor models to the simple first order estimation used in your hand calculation, you can expect the same ro values (correct DC bias taken as granted). Regarding capcitances, you would obviously select a frequency range for your simulation that allows to recognize frequency dependent effects.

Finally, is it expecting too much to aks for a circuit schematic?

 

[cleve]

You could try with sp simulation to see the real part of zp impedance.