brainiac_rus
Newbie level 5
Hello!
First question is about using Xilinx EDK. I use it for implementing axi system with my cores. I don't understand next thing: if i design my core with axi interface and implement it to the axi system, than if i change this core - i think there are two ways - with or without changing inputs and outputs of the core - next i must import new version of my core?
Second question is about verilog language. I have about 3 variants of spi module with different CHPA and CPOL. I want to write one spi module and change CPHA and CPOL in parameters. What type of parameter must be CPOL and CPHA that synthesizer can correctly synthesize definitions such as:
if(...)
sclk <= CPOL;
...
First question is about using Xilinx EDK. I use it for implementing axi system with my cores. I don't understand next thing: if i design my core with axi interface and implement it to the axi system, than if i change this core - i think there are two ways - with or without changing inputs and outputs of the core - next i must import new version of my core?
Second question is about verilog language. I have about 3 variants of spi module with different CHPA and CPOL. I want to write one spi module and change CPHA and CPOL in parameters. What type of parameter must be CPOL and CPHA that synthesizer can correctly synthesize definitions such as:
if(...)
sclk <= CPOL;
...
