2.5v LVDS with 3.3v Reciever

[rmawatson]

Hello,

I just wanted to check if there are likely to be any problems interfacing the following clock fanout ( https://www.ti.com/lit/ds/symlink/sn65lvds104.pdf ) which is 3.3v with 2.5v driver from my FPGA.

The differential specifications seem fine for both reciever and trasmitter

My concern is with the "Fail Safe" 300k pull-ups on the Receiver that will pull the lines high when not driven. Is this going to cause any issues to the driver. the 3.3 v is well within the absolute maximum (3.6) of the drivers device pins, but I don't know if there is any problem at all with the differential driver of the FPGA seeing 3.3v on the pin when it is switched on.

Thanks for any assistance.

 

[FvM]

There's only one LVDS I/O standard, no thing like 2.5V /3.3 V etc. LVDS. In so far each LVDS driver should be interoperable with any LVDS receiver. Specifically, I don't see a problem caused by the pull-up resistors.

 

[KlausST]

Hi,

i don´t expect any problems.

You don´t say what FPGA.
When i remember right then with a Spartan6 the signals for LVDS2.5 and LVDS3.3 are absolutely the same.
The only thing that changes is the VCC voltage of the relating FPGA bank.

I think this is how it should be: The LVDS signals (levels) should not change with the VCC voltage of the devices.

Klaus