19 bit counter in verilog. Is it possible?

[anhnha]

Hi.

I am writing a counter 19 bits in verilog. The problem is that I have never seen such a large counter like that.
Do you think it is possible?
I am new to verilog.
Thanks.

 

[imbichie]

yes, its possible.

 

[vir_1602]

Yes it is possible bt dividing the clock and count less is better approach to count higher counts..

 

[TrickyDicky]

Yes it is possible bt dividing the clock and count less is better approach to count higher counts..

I dont quite understand the message?
Generating clocks from counters should always be avoided.

 

[vir_1602]

hi dick

yes it is normally avoided but i wrote this in power saving prospective .
by this way we can have less no of transition
and such huge counter is required when u want to count a long time period in some block like reset chatter. so it is beneficial to count on slow clock
plz correct me if i am wrong

Thanks and Regds
vir

 

[FvM]

Nobody has been talking about clock, clock speed and timer applications so far. You are discussing "what would it be like if ...".

 

[BartlebyScrivener]

Yes it is possible. There is an explanation of verilog counter design and simulation, and much more, here.

https://www.asic-world.com/verilog/first1.html

 

[vir_1602]

my dear FVm

plz see the 1st post of the anhnna . he has written that he hasn't seen such a large counter, so I was telling where such a large counter can be used at what place and a better altenative

Thanks and Regards
Vir