That is honestly the most ridiculous routing job I've seen in a long time working with FPGAs.
You don't by chance have some really strange XDC constraint for your I/O timing do you?
You should probably post the constraint you are using for that I/O it almost looks like it added delay to meet a minimum delay constraint for a clock to out path.
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You should output the entire path report for this pin and post it, along with the timing constraints used for this pin.
BTW, if you came from ISE land, with UCF files, the input and output constraints are NOT the same for XDC, which uses the synopsys convention. An input constraint in UCF is the allowed delay from pin to FF inside the FPGA. for XDC it's the source's delay from the clock to the FPGA's pin (i.e. the driving components Tco + the propagation delay of the board routing between the source and the FPGA). For and output it's the routing delay + the setup time of the external device. Maybe you are using an absurd delay because it was a UCF constraint instead of an XDC (SDC) style constraint.