jerryzhao said:There are 3 stage pre-amp the last stage is a latch for comparator. The comp is differential input, one end connect cap array output, other end connect the VCM.
There are restet swith in pre-amp, there are output voltage limit diodes in pre-amp. the latch can autozero. But without the offset cancel in comparator as our system is not care the offset.
I test the ADC in low speed, when the SPS less than 10Ksps the jump voltage do not reduce as the sps reduce. 10K-30K SPS the jump voltage increase with the sps speed increase.
Added after 5 minutes:
I simulate the voltage around the VCM, the comparator result is right. We do noise simulation simulation also. so we can test the DNL is 1~2 LSB in most point. only the jump vlotage in when input cross the 1/2 VREF.
jerryzhao said:There 2 section in cap array in ADC, 7bit + 9bit. signal end input. the coupling cap between two section is unit cap, so the LSB section is 127 unit cap.
XYdecode control the thermometer code. the control circuit design by digital designer.
Note that offset does not appear into a total characteristic as a constant offset, because you have to connect two DACs. It degrades dnl and can produce such jumps, which are code dependant.jerryzhao said:I have calculate the mismatch, I do some simulation, all the mismatch or parasitic cap only contribute a offset, not the hysteresis. I am looking for.........
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