is this actually doable in 0.35 um or 0.5 um CMOS nowadays without calibration or trimming ? i do not want to do a sigma-delta ADC for this "threshold" resolution (16 bits, cause it's high, but not too high to keep successive approximation out of choice), can anyone give me suggestions ?
Hey try and design using an integrating architecture. I would suggest a dual slope or a quad slope architecture in order to achieve the required resolution. There are designs using integrating architecture and achieving a 16 bit resolution. Only you should be able to achieve that speed and good component matching. And importantly, the speed is a critereon. I am not sure whether Integrating ADCs achieve such high speeds.
But mostly people prefer sigma delta for these kind of resolutions and
thanks very much, but if you use dual slope, for the case of 9k samples/second, you must have a clock frequency of about 590 MHz (2^16*9000, because you must count down 2^16=65536 times to decide which level the sample is in), which is not quite feasible, is it ?
Before, I designed Sigma-Delta ADC. Sigma-Delta is a better choice to achieve 16-bit (SNR-->96dB) performance. And Sigma-Delta ADC is much easier than other types. Maybe Sigma-Delta ADC is a possibility for you.
is this actually doable in 0.35 um or 0.5 um CMOS nowadays without calibration or trimming ? i do not want to do a sigma-delta ADC for this "threshold" resolution (16 bits, cause it's high, but not too high to keep successive approximation out of choice), can anyone give me suggestions ?