PLL problem - troubleshooting pll problems

[fnx7]

troubleshooting pll problems

Test condition
PLL chip :adf4106
VCO :950MHz~2150MHz
charge pump current:2.5mA
loop bandwidth: 800Hz
PHD frequency(reference frequency):3MHz
loop type type A
test result

I want to konw the probably cause.

Thanks

 

[FvM]

PLL problem??

Most likely inappropriate loop filter + gain. VccPLL stable regulation and decoupling should be checked, too.

 

[fnx7]

Re: PLL problem??

How to understand the inappropriate loop+gain? Could you explain it more detail
Thanks

 

[FvM]

PLL problem??

It's a feedback loop that can become unstable. I think, Analog has tools for loop filter calculation, basic literature discusses the topic as well. You can also tell your loop filter dimensioning and VCO specification, so other forum members can check the stability.

 

[LvW]

Re: PLL problem??

Hi fnx7,

in your own interest , I propose to study some PLL basics first rather than ask someone else for details of stability.
I think if somebody is going to design a PLL he at least should know the meaning and the function of the loop filter and the role of the loop gain as far as the function of the loop as well as stability is concerned. Otherwise you could ask someone else to do the job.

 

[fnx7]

Re: PLL problem??

I calculated the loop filter values using Analog Device PLLsim3.0 loop bandwidth is 800Hz, phase margin is 43 degree. Perhaps the phase margin simulation is not same as measurement.

 

[RFDave]

Re: PLL problem??

You've really zoomed in on the signal, with a 10 kHz bandwidth. This looks like your PLL is being modulated, as you have symmetrical sidebands. I'd take a look at the DC bypassing on your VCO. If you are tuning over a 1 GHz range with your VCO, it's got to be very sensitive to noise on the tuning control line.

Dave
www.keystoneradio.com

 

[fnx7]

Re: PLL problem??

When lock at 1150~1650MHz it is ok. From 1750~2050MHz it seems unstable.

 

[VSWR]

Re: PLL problem??

At which VCO frequency did you get 43° phase margin? The phase margin may vary with VCO frequency as Kvco may vary.

I calculated the loop filter values using Analog Device PLLsim3.0 loop bandwidth is 800Hz, phase margin is 43 degree. Perhaps the phase margin simulation is not same as measurement.

When lock at 1150~1650MHz it is ok. From 1750~2050MHz it seems unstable.

 

[fnx7]

Re: PLL problem??

Thanks
I changed the frequency setting in simulation, and get a new loop filter values.
When the loop bandwidth is increased a bit, the loop is stable.

 

[bengilbert]

Re: PLL problem??

There are many reasons why you are getting these problems and until you solve the problem you really won't know what the source of the problem is. You might find the solution to the problem **broken link removed**.